MAX174ACPI Просмотр технического описания (PDF) - Maxim Integrated

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MAX174ACPI

Industry-Standard, Complete 12-Bit ADCs

Maxim Integrated 

MAX174/MX574A/MX674A

Industry-Standard, Complete 12-Bit ADCs

Timing and Control

Convert Start Timing—Full Control Mode

R/C must be low before asserting both CE and CS. If it

is high, a brief read operation occurs possibly resulting

in system bus contention. To initiate a conversion, use

either CE or CS. CE is recommended since it is shorter

by one propagation delay than CS and is the faster input

of the two. CE is used to begin the conversion in Figure 4.

The STS output is high during the conversion indicating

the ADC is busy. During this period, additional convert

start commands will be ignored, so that the conversion

cannot be prematurely terminated or restarted. However,

if the state of A0 is changed after the beginning of the

conversion, any additional start conversion transitions

will latch the new state of A0, possibly resulting in an

incorrect conversion length (8 bits vs. 12 bits) for that

conversion.

Read Timing—Full Control Mode

Figure 5 illustrates the read-cycle timing. While reading

data, access time is measured from when CE and R/C

are both high. Access time is extended 10ns if CS is used

to initiate a read.

CE

CS

R/C

A0

STS

D0–D11

tHEC

tHSC

tSSC

tHRC

tSRC

tHAC

tSAC

tDSC

tC

HIGH IMPEDANCE

Figure 4. Convert Start Timing

CE

tSSR

CS

tSRR

R/C

tSAR

A0

STS

D0–D11

tDD

HIGH IMPEDANCE

Figure 5. Read Timing

tHSR

tHRR

tHAR

tHD,tHL

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