MC68SEC000AA10 Просмотр технического описания (PDF) - Freescale Semiconductor
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MC68SEC000AA10 Datasheet PDF : 8 Pages
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Freescale Semiconductor, Inc.
PROCESSOR
STATUS
VCC
GND
CLK
FC0
FC1
FC2
A23-A0
ADDRESS BUS
MC68SEC000
D15-D0
AS
R/W
UDS
LDS
DTACK
DATA BUS
ASYNCHRONOUS
BUS CONTROL
BR
BUS ARBITRATION
BG
CONTROL
SYSTEM
CONTROL
BERR
RESET
HALT
MODE
IPL0
IPL1
IPL2
AVEC
INTERRUPT
CONTROL
Figure 2. Functional Signal Groups
Address Bus (A23-A0)
This 24-bit, unidirectional, three-state bus can address 16 Mbytes of data. It provides the address for bus
operation during all cycles except interrupt cycles. During interrupt cycles, A3, A2, and A1 reflect the level
of the interrupt being serviced, while A23-A4 and A0 are set to a logic high.
Data Bus (D15-D0)
This 16-bit, bidirectional, three-state bus is the general-purpose data path. Using the mode pin, you can
statically select either 8- or 16-bit modes for data transfer.
Asynchronous Bus Control
Asynchronous data transfers are handled using the following control signals: address strobe (AS), read/
write (R/W), upper and lower data strobes (UDS, LDS), and data transfer acknowledge (DTACK). The
address strobe signal indicates there is a valid address on the address bus. Read/write defines the data bus
transfer as a read or write cycle. The data strobes control the flow of data on the data bus and the data
transfer acknowledge indicates that the data transfer is complete.
Bus Arbitration Control
In multiple bus master systems, the bus arbitration circuit determines which device will be the bus master.
The bus request (BR) indicates that an external device requires bus mastership. A bus grant (BG) indicates
to all other potential bus master devices that the controller will release bus control at the end of the current
bus cycle.
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MC68SEC000 PRODUCT INFORMATION
MOTOROLA
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