AD9870 Просмотр технического описания (PDF) - Analog Devices
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AD9870 Datasheet PDF : 20 Pages
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AD9870
CLKOUT
FS
DOUT
I15
I0
Q15
Q14
Q0
SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0
CLKOUT
FS
DOUT
I15
I0
Q15
Q14
Q0
G15
SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC = 0
G14
G0
CLKOUT
FS
HI-Z
DOUT
START
BIT
I15
START
I8
STOP
BIT
I7
BIT
START
I0
STOP
BIT
Q15
BIT
IDLE (HIGH) BITS
SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0
SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0: AS ABOVE, BUT FS IS LOW
CLKOUT
FS
DOUT
I15
I0
Q15
Q14
Q0
SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0
Figure 2. SSI Timing for Several SSICR Settings
The two optional bytes are output if the EAGC bit of SSICRA
is set. The first byte contains the eight most significant bits of
the AGC DAC setting while the second byte contains a 2-bit
overload field, a 2-bit reset field, a 2-bit large-signal field, a zero
bit, and a trailing high bit. The overload, reset, and large-signal
fields contain the number of overload, reset, and large-signal
events since the last report, respectively, saturating at three
should the number of events equal or exceed this amount. The
two optional bytes follow the I and Q data as a 16-bit word
provided the AAGC bit of SSICRA is not set. If the AAGC bit
is set, the two bytes follow the I and Q data in an alternating
fashion. In this “alternate AGC data” mode, the LSB of the
byte containing the AGC DAC setting is zero; the LSB of the
byte containing reset/overload information is always a one.
Figure 3 illustrates the fields of the SSI data frames.
EAGC = 0, AAGC = X: 32 DATA BITS
I (15:0)
Q (15:0)
EAGC = 1, AAGC = 0: 48 DATA BITS
I (15:0)
Q (15:0)
AGC (7:0)
EAGC = 1, AAGC = 1: 40 DATA BITS
I (15:0)
Q (15:0)
I (15:0)
Q (15:0)
AGC (7:1) 0
1
OVERLOAD COUNT
RESET COUNT
DON’T CARE
FGM
Figure 3. SSI Frame Structure
1
SAME
–8–
REV. 0
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