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TDA9143/N1

I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor

Preliminary specification

TDA9143

FEATURES

• Multi-standard colour decoder and sync processor for

PAL, NTSC and SECAM

• PALplus helper blanking and EDTV-2 blanking

• I2C-bus controlled

• I2C-bus addresses hardware selectable

• Pin compatible with TDA9141

• Alignment free

• Few external components

• Designed for use with baseband delay lines

• Integrated video filters

• Adjustable luminance delay

• Noise detector with I2C-bus read-out

• Norm/no_norm detector with I2C-bus read-out

• CVBS or Y/C input, with automatic detection possibility

• CVBS output, provided I2C-bus address 8A is used

• Vertical divider system

• Two-level sandcastle signal

• VA synchronization pulse (3-state)

• HA synchronization pulse or clamping pulse CLP

input/output

• Line-locked clock output (6.75 MHz or 6.875 MHz) or

stand-alone I2C-bus output port

• Stand-alone I2C-bus input/output port

• Colour matrix and fast YUV switch

• Comb filter enable input/output with subcarrier

frequency

• Internal bypass mode of external delay line for NTSC

applications

• Low power standby mode with 3-state YUV outputs

• Fast blanking detector with I2C-bus read-out

• Blanked or unblanked sync on Yout by I2C-bus bit BSY

• Internal MACROVISION gating for the horizontal PLL

enabled by bus bit EMG.

GENERAL DESCRIPTION

The TDA9143 is an I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor with blanking

facilities for PALplus and EDTV-2 signals. The TDA9143

has been designed for use with baseband chrominance

delay lines, and has a combined subcarrier

frequency/comb filter enable signal for communication

with a PAL/NTSC comb filter.

The IC can process both CVBS input signals and Y/C input

signals. The input signal is available on an output pin, in

the event of a Y/C signal, it is added into a CVBS signal.

The sync processor provides a two-level sandcastle, a

horizontal pulse (CLP or HA pulse, bus selectable) and a

vertical (VA) pulse. When the HA pulse is selected, a

line-locked clock (LLC) signal is available at the output port

pin (6.75 MHz or 6.875 MHz).

A fast switch can select either the internal Y signal with the

UV input signals, or YUV signals made of the RGB input

signals. The RGB input signals can be clamped with either

the internal or an external clamping signal.

Two pins with an input/output port and an output port of the

I2C-bus are available.

The I2C-bus address of the TDA9143 is hardware

programmable.

ORDERING INFORMATION

TYPE

NUMBER

NAME

TDA9143 SDIP32

PACKAGE

DESCRIPTION

plastic shrink dual in-line package; 32 leads (400 mil)

VERSION

SOT232-1

1996 Jan 17

2

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