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SPT7760BIK Просмотр технического описания (PDF) - Signal Processing Technologies

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производитель
SPT7760BIK
SPT
Signal Processing Technologies SPT
SPT7760BIK Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
TYPICAL INTERFACE CIRCUIT
The circuit in figure 1 is intended to show the most elaborate
method of achieving the least error by correcting for integral
linearity, input induced distortion and power supply/ground
noise. This is achieved by the use of external reference
ladder tap connections, input buffer and supply decoupling.
Please contact the factory for the SPT7760 evaluation board
applications note that contains more details on interfacing the
SPT7760. The function of each pin and external connections
to other components is as follows:
VEE, AGND, DGND
VEE is the supply pin with AGND as ground for the device. The
power supply pins should be bypassed as close to the device
as possible with at least a .01 µF ceramic capacitor. A 1 µF
tantalum can also be used for low frequency suppression.
DGND is the ground for the ECL outputs and is to be
referenced to the output pulldown voltage and appropriately
bypassed as shown in figure 5.
VIN (ANALOG INPUT)
There are two analog input pins that are tied to the same point
internally. Either one may be used as an analog input sense
and the other for input force. This is convenient for testing the
source signal to see if there is sufficient drive capability. The
pins can also be tied together and driven by the same source.
The SPT7760 is superior to similar devices due to a pream-
plifier stage before the comparators. This makes the device
easier to drive because it has constant capacitance and
induces less slew rate distortion.
(VRM) and AGND (VRT force and sense). The reference pins
and tap can be driven by op amps as shown in figure 1 or VRM
may be bypassed for limited temperature operation. These
voltage inputs can be bypassed to AGND for further noise
suppression if so desired.
Table I - Output Coding
VIN
> -0.5 LSB
D8 D7 • • • D0
1 10000000
-0.5 LSB
1 10000000
0 10000000
-1.5 LSB
0 10000000
0 10000001
-1.0 V
0 11000000
0 01000000
-2.0 V+ 1/2 LSB
0 00000001
0 00000000
< (-2.0 V +1/2 LSB)
0 00000000
CLK, CLK (CLOCK INPUTS)
The clock inputs are designed to be driven differentially with
ECL levels. The duty cycle of the clock should be kept at 50%
to avoid causing larger second harmonics. If this is not
important to the intended application, then duty cycles other
than 50% may be used.
D0 TO D8, DR, NDR (A AND B)
The digital outputs can drive 50 to ECL levels when pulled
down to -2 V. When pulled down to -5.2 V, the outputs can
drive 130 to 1 kloads. All digital outputs are grey code with
the coding as shown in table 1. SPT recommends using
differential receivers on the outputs of the data ready lines to
ensure the proper output rise and fall times.
VRBF, VRBS, VRTF, VRTS, VRM
(REFERENCE INPUTS)
There are two reference inputs and one external reference
voltage tap. These are -2 V (VRB force and sense), mid-tap
Indicates the transition between the two codes
THERMAL MANAGEMENT
The typical thermal impedance has been measured as fol-
lows:
ΘCA = +17 °C/W in still air with no heat sink
We highly recommend that a heat sink be used for this device
with adequate air flow to ensure rated performance of the
device. We have found that a Thermalloy 17846 heat sink
with a minimum air flow of 1 meter/second (200 linear feet per
minute) provides adequate thermal performance under labo-
ratory tests. Application specific conditions should be taken
into account to ensure that the device is properly heat sinked.
SPT
5
SPT7760
3/10/97

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