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LF3310QC12

Horizontal / Vertical Digital Image Filter

LOGIC Devices 

DEVICES INCORPORATED

LF3310

Horizontal / Vertical Digital Image Filter

FIGURE 10. DATA REVERSAL

TXFR

LIFO A

LIFO B

When the filter is configured for an

odd number of taps, the data which

will appear at the output of the last

I/D Register in the forward data path

on the next clock cycle is fed into the

first I/D Register in the reverse data

path. Bit 5 in Configuration Register

1 configures the filter for an even or

odd number of taps.

Data Reversal

Data reversal circuitry is placed after

the multiplexer which routes data

from the forward data path to the

reverse data path (see Figure 10).

When decimating, the data stream

must be reversed in order for data to

be properly aligned at the inputs of

the ALUs. When data reversal is

enabled, the circuitry uses a pair of

LIFOs to reverse the order of the data

sent to the reverse data path. When

TXFR goes LOW, the LIFO sending

data to the reverse data path becomes

the LIFO receiving data from the

forward data path, and the LIFO

receiving data from the forward data

path becomes the LIFO sending data

to the reverse data path. The device

must see a HIGH to LOW transition

of TXFR in order to switch LIFOs. If

decimating by N, TXFR should go low

once every N clock cycles. When data

reversal is disabled, the circuitry

functions like an I/D Register. When

feeding interleaved data through the

filter, data reversal should be

disabled. Bit 6 of Configuration

Register 1 enables or disables data

reversal.

Horizontal Rounding

The horizontal filter output may be

rounded by adding the contents of

one of the sixteen horizontal round

registers to the horizontal filter output

FIGURE 11. HORIZONTAL AND VERTICAL ROUND/SELECT/LIMIT CIRCUITRY

VRSL3-0

4

DATA IN

32

DATA IN

32

HRSL3-0

4

When interleaved data is fed through

the device and an even tap filter is

desired, the filter should be config-

ured for an even number of taps (Bit 5

of CR1 set to “0”) and the I/D Regis-

ter length should match the number

of data sets interleaved together.

When interleaved data is to be fed

through the device and an odd tap

filter is desired, the filter should be

set to Odd-Tap Interleave Mode. Bit 0

of Configuration Register 1 configures

the filter for Odd-Tap Interleave

Mode. When the filter is configured

for Odd-Tap Interleave Mode, data

from the next to last I/D Register in

the forward data path is fed into the

first I/D Register in the reverse data

path.

When the filter is configured for an

odd number of taps (interleaved or

non-interleaved modes), the filter is

structured such that the center data

value is aligned simultaneously at the

A and B inputs of the last ALU in the

forward data path. In order to

achieve the correct result, the user

must divide the coefficient by two.

VERTICAL RSL

32

RND

32

5

SELECT

12

24

LIMIT

12

DATA OUT

32

RND

32

5

SELECT

12

24

LIMIT

12

DATA OUT

HORIZONTAL RSL

Video Imaging Products

8

11/08/2001-LDS.3310-H

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