78Q2132 Просмотр технического описания (PDF) - TDK Corporation
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78Q2132 Datasheet PDF : 36 Pages
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78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
MII (continued)
PIN
MDC
MDIO
PHYAD[4:0]
80-PIN 64-PIN TYPE
22
18
I
21
17
I/O
14-18 12-16
I
DESCRIPTION
MANAGEMENT DATA CLOCK: MDC is the clock used for
transferring data via the MDIO pin.
MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-
directional port used to access management registers within the
78Q2132. This pin requires an external pull-up resistor as
specified in IEEE-802.3.
PHY ADDRESS: Allows 31 configurable PHY addresses. The
78Q2132 always responds to data transactions via the MII
interface when the PHYAD bits are all zero independent of the
logic levels of the PHYAD pins.
CONTROL AND STATUS
NAME
RST
80-PIN 64-PIN
6
4
PWRDN
ISO
7
5
57
N/A
ISODEF
ANEGA
58
N/A
66
54
TYPE
I
I
I
I
I
DESCRIPTION
RESET: When pulled low the pin resets the chip. There are 3
other ways to reset the chip:
i)
through the internal power-on-reset (activated when
the chip is being powered up)
ii)
through the MII register bit MR 0.15
iii)
upon exiting power-down mode
Refer to the Reset Modes section for more details.
POWER-DOWN: The 2132 may be placed in a low power
consumption state by setting this signal to logic high. While in
power-down state, the 2132 still responds to management
transactions. The same power-down state can also be achieved
through the PWRDN bit in the MII register MR0.11.
ISOLATE: When set to logic one, the 2132 will present a high
impedance on its MII output pins. This allows for multiple PHYs to be
attached to the same MII interface. When the 2132 is isolated, it still
responds to management transactions. The same high impedance
state can also be achieved through the ISO bit in the MII register
MR0.10. This pin also sets the default of the ISO bit.
ISOLATE DEFAULT: This pin determines the power-up/reset
default of the ISO bit, MR0.10. If it is connected to VDD, ISO
bit will have a default value of 1. If it is connected to GND, ISO
bit will have a default value of 0.
AUTO-NEGOTIATION ABILITY: Strapped to logic high to allow
auto-negotiation function. When strapped to logic low, auto-
negotiation logic is disabled and manual technology selection
is done through TECH[2:0]. This pin is reflected as ANEGA bit
MR1.3.
7
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