78Q2132 Просмотр технического описания (PDF) - TDK Corporation
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78Q2132 Datasheet PDF : 36 Pages
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78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
PIN DESCRIPTION
LEGEND
TYPE DESCRIPTION
A Analog Pin
O Digital Output
S Supply
TYPE DESCRIPTION
I Digital Input
I/O Digital Bi-directional Pin
OZ Tri-stateable digital output
MII (MEDIA INDEPENDENT INTERFACE)/ GPSI (GENERAL PURPOSE SERIAL INTERFACE)
PIN
TX_CLK
(GPSI & MII)
80-PIN 64-PIN TYPE
33
27
OZ
TX_EN
(GPSI & MII)
34
28
I
TXD[3:0]
40-37 32-29
I
(TXD[0] = TXDAT
in GPSI mode)
TX_ER
CRS
(GPSI & MII)
32
26
I
42
34
OZ
COL
(CLSN in GPSI
mode)
41
33
OZ
RX_CLK
(GPSI & MII)
30
24
OZ
RX_DV
29
23
OZ
RXD[3:0]
23-26 19-22 OZ
(RXD[0] = RXDAT
in GPSI mode)
RX_ER
31
25
OZ
DESCRIPTION
TRANSMIT CLOCK: TX_CLK is a continuous clock which
provides a timing reference for the TX_EN, TX_ER and TXD[3:0]
signals from the MAC. The clock frequency is 2.5MHz in 10baseT
mode and bursty in HomeLAN mode. When the GPSI port is
selected, this is the transmit clock for the General Purpose Serial
Interface. This pin is tri-stated in isolate mode.
TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate
that valid data for transmission is present on the TXD[3:0] pins.
This pin is shared for both the GPSI interface and the MII interface.
TRANSMIT DATA: When the MII port is selected via the MII_EN
select pin, TXD[3:0] receives data from the MAC for transmission on
a nibble basis. This data is captured on the rising edge of TX_CLK
when TX_EN is high. When the GPSI port is selected, TXD[0] is
used for the serial transmit data, TXDAT.
RESERVED
CARRIER SENSE: CRS is high whenever a non-idle condition
exists on either the transmitter or the receiver. When the GPSI port
is selected, this pin becomes the CRS pin of the GPSI. This pin is
tri-stated in isolate mode.
COLLISION: : When the MII port is selected via the GPSI/MII select
pin, COL is asserted high when a collision has been detected on the
media. In 802.3 mode COL is also used for the SQE test function.
When the GPSI port is selected, this pin becomes the CLSN pin of
the GPSI. This pin is tri-stated in isolate mode.
RECEIVE CLOCK: RX_CLK is a continuous clock which
provides a timing reference to the MAC for the RX_DV, RX_ER
and RXD[3:0] signals. When the GPSI port is selected, this pin
becomes the RX_CLK pin of the GPSI. The clock frequency is
2.5MHz in 10baseT mode and bursty in HomeLAN mode. This
pin is tri-stated in isolate mode.
RECEIVE DATA VALID: RX_DV is asserted high to indicate that
valid data is present on the RXD[3:0] pins. It transitions high
when the start-of-frame delimiter (SFD) is detected. This pin is
tri-stated in isolate mode.
RECEIVE DATA: When the MII port is selected via the MII_EN
select pin, received data is provided to the MAC via RXD[3:0].
When the GPSI port is selected, RXD[0] is used for the serial
received data, RXDAT. This pin is tri-stated in isolate mode.
RESERVED
6
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