M58LV064A, M58LV064B
Figure 9. Example Burst Address Advance and Burst Abort operations
01
K
Address
Inputs
Q1
L
B
Data Inputs/
Outputs
X-2
X
X+2
X+4
X+6
X+8
X+10
X+12
tBLKH
tBHKH
tBHKH
tBHKH
Q1
Q2
Q3
Q3
Q4
Q4
Q4
AI03457b
Note: 1. In this example the Burst Configuration Register is set with M2-M0 = 010 (Burst Length = 8 Words), M6 = 1 (Valid Clock Edge =
Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 1 (Y-Latency = 2), M14-M11 = 0011 (X-Latency =
8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.
2. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock
cycles, starting from the first read are not considered.
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