M58LV064A Просмотр технического описания (PDF) - STMicroelectronics

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M58LV064A

64 Mbit (4Mb x16 or 2Mb x32, Uniform Block, Burst) 3V Supply Flash Memories

STMicroelectronics 

M58LV064A, M58LV064B

first. The Data Inputs/Outputs are latched by the

Command Interface on the rising edge of Chip En-

able or Write Enable, whichever occurs first. Out-

put Enable must remain High, VIH, during the

whole Asynchronous Bus Write operation. See

Figures 16 and 18 Asynchronous Latch Controlled

Write AC Waveforms, and Tables 20 and 21,

Asynchronous Write and Latch Controlled Write

AC Characteristics, for details of the timing re-

quirements.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when the Output Enable

is High.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high imped-

ance state regardless of Output Enable or Write

Enable. The Supply Current is reduced to the

Standby Supply Current, IDD1.

During Program or Erase operations the memory

will continue to use the Program/Erase Supply

Current, IDD3, for Program or Erase operations un-

til the operation completes.

Automatic Low Power. If there is no change in

the state of the bus for a short period of time during

Asynchronous Bus Read operations the memory

enters Auto Low Power mode where the internal

Supply Current is reduced to the Auto-Standby

Supply Current, IDD5. The Data Inputs/Outputs will

still output data if a Bus Read operation is in

progress.

Automatic Low Power is only available in Asyn-

chronous Read modes.

Power-Down. The memory is in Power-Down

mode when Reset/Power-Down, RP, is Low. The

power consumption is reduced to the Power-Down

level, IDD2, and the outputs are high impedance,

independent of Chip Enable, Output Enable or

Write Enable.

Table 2. Asynchronous Bus Operations

Bus Operation

Step

E G W RP M3(2) L

Asynchronous Bus Read

VIL VIL VIH High 0

X

Asynchronous Latch

Controlled Bus Read

Address Latch

Read

VIL VIL VIH High 1

VIL

VIL VIL VIH High 1 VIH

Asynchronous Page Read

VIL VIL VIH High 0

X

Asynchronous Bus Write

VIL VIH VIL High X VIL

Asynchronous Latch

Controlled Bus Write

Address Latch

VIL VIH VIL High X VIL

Output Disable

VIL VIH VIH High X

X

Standby

VIH X X High X

X

Power-Down

X X X VIL X

X

Note: 1. X = Don’t Care VIL or VIH. High = VIH or VHH.

2. M15 = 1, Bits M15 and M3 are in the Burst Configuration Register.

A1-A22

Address

Address

X

Address

Address

DQ0-DQ31

Data Output

High Z

Data Output

Data Output

Data Input

Address Data Input

X

High Z

X

High Z

X

High Z

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