MT90820 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

Номер в каталоге

Компоненты Описание

производитель

MT90820

Large Digital Switch

Zarlink Semiconductor Inc 

MT90820

Data Sheet

Wide Frame Pulse (WFP) Frame Alignment Timing

When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is

4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. The timing relationship between CLK, HCLK and the

frame pulse is defined in Figure 12.

When WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers may

still be programmed to compensate for the varying frame delays on the serial input streams.

Switching Configurations

The MT90820 maximum non-blocking switching configurations is determined by the data rates selected for the

serial inputs and outputs. The switching configuration is selected by two DR bits in the IMS register. See Table 8

and Table 9.

2.048 Mb/s Serial Links (DR0=0, DR1=0)

When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each

having 32 64 Kbit/s channels each. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking

capacity of 512 x 512 channels.

4.096 Mb/s Serial Links (DR0=1, DR1=0)

When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each

having 64 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking

capacity of 1,024 x 1,024 channels.

8.192 Mb/s Serial Links (DR0=0, DR1=1)

When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each

having 128 64 Kbit/s channels each. This mode requires a CLK of 16.384 MHz and allows a maximum non-

blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship

between different serial data rates and the master clock frequencies.

Serial Interface

Data Rate

Master Clock

Required

(MHz)

Matrix Channel

Capacity

2 Mb/s

4 Mb/s

8 Mb/s

4.096

8.192

16.384

512 x 512

1,024 x 1,024

2,048 x 2,048

Table 1 - Switching Configuration

8

Zarlink Semiconductor Inc.

Share Link: