MT90820AP1 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT90820AP1 Datasheet PDF : 37 Pages
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MT90820
Data Sheet
Read/Write Address:
Reset value:
03H for FOR0 register,
04H for FOR1 register,
05H for FOR2 register,
06H for FOR3 register,
0000H for all FOR registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR0 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR1 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
FOR2 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR3 register
Name
(Note 1)
Description
OFn2, OFn1, OFn0
Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes to
recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input frame offset
can be selected to +4 clock periods from the point where the external frame pulse input signal is
applied to the F0i input of the device. See Figure 4.
DLEn
Data Latch Edge.
ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock falling edge is at the 3/4 of the bit cell.
GCI mode:
DLEn =0, if clock falling edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock rising edge is at the 3/4 of the bit cell.
Note 1: n denotes an input stream number from 0 to 15.
Table 11 - Frame Input Offset (FOR) Register Bits
Input Stream
Offset
No clock period shift (Default)
Measurement Result from
Frame Delay Bits
FD11 FD2 FD1 FD0
1
0
0
0
OFn2
0
Corresponding
Offset Bits
OFn1
0
OFn0
0
DLEn
0
17
Zarlink Semiconductor Inc.
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