MT90820AP1 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT90820AP1 Datasheet PDF : 37 Pages
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MT90820
Data Sheet
cycle of channel 31 through CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection
memory is output on the second clock cycle of channel 31 via CSTo pin.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory location enables (if high) or disables (if
low) the output drivers for an individual ST-BUS output stream and channel. See Table 5 for detail.
The message channel (MC) bit of the connection memory enables (if high) an associated ST-BUS output channel in
message mode. If the MC bit is low, the contents of the stream address bit (SAB) and the channel address bit
(CAB) of the connection memory defines the source information (stream and channel) of the time-slot that will be
switched to the output. When message mode is enabled, only the lower half (8 least significant bits) of the
connection memory is transferred to the ST-BUS outputs.
Bit V/C (Variable/Constant Delay) of each connection memory location allows the per-channel selection between
variable and constant throughput delay modes.
If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input
channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel
m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo
n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback
function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally.
Initialization of the MT90820
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all ST-BUS outputs in a high impedance state until the microprocessor has initialized the
switching matrix.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch, and put all other channels into a high impedance state. This procedure prevents two ST-BUS
outputs from driving the same stream simultaneously. When this process is complete, the microprocessor
controlling the matrices can bring the ODE pin or OSB bit high to relinquish the high impedance state control to the
OE bit in the connection memory.
A7
(Note 1)
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0 Control Register, CR
0
0
0
0
0
0
0
1 Interface Mode Selection Register, IMS
0
0
0
0
0
0
1
0 Frame Alignment Register, FAR
0
0
0
0
0
0
1
1 Frame Input Offset Register 0, FOR0
0
0
0
0
0
1
0
0 Frame Input Offset Register 1, FOR1
0
0
0
0
0
1
0
1 Frame Input Offset Register 2, FOR2
0
0
0
0
0
1
1
0 Frame Input Offset Register 3, FOR3
1
0
0
0
0
0
0
0 Ch 0
1
0
0
0
0
0
0
1 Ch 1
1
0
0
.
.
.
.
..
1
0
0
1
1
1
1
0 Ch 30
1
0
0
1
1
1
1
1 Ch 31
(Note 2)
12
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