50S116T-5 Просмотр технического описания (PDF) - CERAMATE TECHNICAL
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50S116T-5 Datasheet PDF : 42 Pages
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50S116T
SDRAM
edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the
CAS Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued
during a full page burst write operation, then any residual data from the burst write cycle will be
ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 1.
Table 1 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BURST LENGTH
BL = 2 (disturb address is A0)
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in
the sequence shown in Table 2.
Table 2 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BUST LENGTH
BL = 2
BL = 4
BL = 8
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.20,2002
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