50S116T-7 Просмотр технического описания (PDF) - CERAMATE TECHNICAL

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50S116T-7

512K x 2 BANKS x 16 BITS SDRAM

CERAMATE TECHNICAL 

50S116T

SDRAM

Auto Precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto precharge function is

entered. During auto precharge, a Read Command will execute as normal with the exception that the

active bank will begin to precharge automatically before all burst read cycles have been completed.

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto precharge can not be interrupted before the entire burst

operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a

read or write cycle with auto precharge. Once the precharge operation has started, the bank cannot be

reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto Precharge command is

illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write

with Auto Precharge function is initiated. The SDRAM automatically enters the precharge operation

one clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank

undergoing auto precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as

tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto precharge Command, the interval

between the Bank Activate Command and the beginning of the internal precharge operation must

satisfy tRAS(min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS , RAS and WE are low and CAS is high at the

rising edge of the clock. The Precharge Command can be used to precharge each bank separately or

all banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be

precharged when the command is issued. After the Precharge Command is issued, the precharged

bank must be reactivated before a new read or write access can be executed. The delay between the

Precharge Command and the Activate Command must be greater than or equal to the Precharge time

(tRP).

Self Refresh Command

The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE

high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.

Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are

disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will

exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after

tRC from the end of Self Refresh command.

If, during normal operation, Auto Refresh cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 4,096 Auto Refresh cycles should be completed just prior to entering and just

after exiting the Self Refresh mode.

Power-down Mode

The Power-down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power-down mode does not perform any refresh operations;

therefore the device can not remain in Power-down mode longer than the Refresh period (tREF) of the

device.

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Tel:886-3-3214525

Fax:886-3-3521052

Page 10 of 42

Email: server@ceramate.com.tw

Http: www.ceramate.com.tw

Rev 1.0 Aug.20,2002

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