IDT70V05L15J(2000) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT70V05L15J Datasheet PDF : 22 Pages
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IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
51 50 48 46 44 42 40 38 36
11
A5L A4L A2L A0L BUSYL M/S INTR A1R A3R
53 52 49 47 45 43 41 39 37 35 34
10 A7L A6L A3L A1L INTL GND BUSYR A0R A2R A4R A5R
55 54
09 A9L A8L
32 33
A7R A6R
57 56
08 A11L A10L
30 31
A9R A8R
59 58
07 VCC A12L
61 60
06 N/C N/C
63 62
05 SEML CEL
IDT70V05G
G68-1(4)
68-Pin PGA
Top View(5)
28 29
A11R A10R
26 27
GND A12R
24 25
N/C N/C
65 64
04 OEL R/WL
22 23
SEMR CER
67 66
03 I/O0L N/C
20 21
OER R/WR
68 1
3
5
7
9
11 13 15 18 19
02 I/O1L I/O2L I/O4L GND I/O7L GND I/O1R VCC I/O4R I/O7R N/C
2
4
6
8
10 12 14 16 17
,
01
I/O3L I/O5L I/O6L VCC I/O0R I/O2R I/O3R I/O5R I/O6R
A
B
C
D
E
FG
H
J
K
L
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2941 drw 04
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Names
Left Port
Right Port
Names
CEL
R/WL
OEL
A0L - A12L
CER
R/WR
OER
A0R - A12R
Chip Enable
Read/Write Enable
Output Enable
Ad d re ss
I/O0L - I/O7L
SEML
INTL
BUSYL
I/O0R - I/O7R
SEMR
INTR
BUSYR
M/S
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
VCC
GND
Po we r
Ground
2941 tbl 01
6.342
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