IDT70V07L(1996) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT70V07L
(Rev.:1996)

HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V07S/L

HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,4,5)

ADDR"A"

W R/ "A"

DATAIN "A"

tAPS(1)

ADDR"B"

BUSY"B"

DATAOUT "B"

tWC

MATCH

tWP

tDW

tDH

VALID

MATCH

tBDA

tWDD

tDDD (3)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

tBDD

VALID

2943 drw 13

TIMING WAVEFORM OF WRITE WITH BUSY

WR/ "A"

BUSY"B"

tWP

tWB( 3 )

WR/ "B"

(2)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.

tWH ( 1 )

2943 drw 14

6.37

11

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