IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Waveform of Read Cycles(5)
ADDR
CE
OE
tRC
tAA(4)
tACE (4)
tAOE (4)
Industrial and Commercial Temperature Ranges
R/W
DATAOUT
BUSYOUT
tLZ (1)
(4)
VALID DATA
tBDD(3,4)
tOH
tHZ(2)
2942 drw 07
NOTES:
1. Timing depends on which signal is asserted las OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.942