IDT70V06L Просмотр технического описания (PDF) - Integrated Device Technology
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IDT70V06L Datasheet PDF : 23 Pages
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IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Industrial and Commercial Temperature Ranges
51 50 48 46 44 42 40 38 36
11
A5L A4L A2L A0L BUSYL M/S INTR A1R A3R
53 52 49 47 45 43 41 39 37 35 34
10 A7L A6L A3L A1L INTL VSS BUSYR A0R A2R A4R A5R
55 54
09 A9L A8L
32 33
A7R A6R
57 56
08 A11L A10L
59 58
07 VDD A12L
61 60
06 N/C A13L
63 62
05 SEML CEL
IDT70V06G
G68(4)
68-Pin PGA
Top View(5)
30 31
A9R A8R
28 29
A11R A10R
26 27
VSS A12R
24 25
N/C A13R
65 64
04 OEL R/WL
22 23
SEMR CER
67 66
03 I/O0L N/C
68 1
3
5
02 I/O1L I/O2L I/O4L VSS
7
9
I/O7L VSS
20 21
OER R/WR
11 13 15 18 19
I/O1R VDD I/O4R I/O7R N/C
2
4
6
8
10 12 14 16 17
01
I/O3L I/O5L I/O6L VDD I/O0R I/O2R I/O3R I/O5R I/O6R
A
B
C
D
E
F
G
H
J
K
L
INDEX
2942 drw 04
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A13L
A0R - A13R
Address
I/O0L - I/O7L
I/O0R - I/O7R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VDD
Power (3.3V)
VSS
Ground (0V)
2942 tbl 01
6.342
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