IDT70T659S008DRI Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

производитель

IDT70T659S008DRI

HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

Integrated Device Technology 

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

CE0L, CE1L

R/WL

CE0R, CE1R

R/WR

OEL

A0L - A17L(1)

OER

A0R - A17R(1)

I/O0L - I/O35L

I/O0R - I/O35R

SEML

SEMR

INTL

INTR

BUSYL

BUSYR

BE0L - BE3L

BE0R - BE3R

VDDQL

VDDQR

OPTL

OPTR

ZZL

ZZR

M/S

VDD

VSS

TDI

TDO

TCK

TMS

TRST

Names

Chip Enables (Input)

Read/Write Enable (Input)

Output Enable (Input)

Address (Input)

Data Input/Output

Semaphore Enable (Input)

Interrupt Flag (Output)

Busy Flag (Output)

Byte Enables (9-bit bytes) (Input)

Power (I/O Bus) (3.3V or 2.5V)(2) (Input)

Option for selecting VDDQX(2,3) (Input)

Sleep Mode Pin(4) (Input)

Master or Slave Select (Input)(5)

Power (2.5V)(2) (Input)

Ground (0V) (Input)

Test Data Input

Test Data Output

Test Logic Clock (10MHz) (Input)

Test Mode Select (Input)

Reset (Initialize TAP Controller) (Input)

5632 tbl 01

NOTES:

1. Address A17x is a NC for IDT70T659.

2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/OX.

3. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are

not affected during sleep mode. It is recommended that boundry scan not be

operated during sleep mode.

5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master

(M/S=VIH).

6

Share Link: