ATF2500C Просмотр технического описания (PDF) - Atmel Corporation

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ATF2500C

ATF2500C CPLD Family Datasheet

Atmel Corporation 

4. Power-up Reset

The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed

slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will

depend on the polarity of the output buffer.

This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in

the system, the following conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin or terms high, and

3. The clock pin, and any signals from which clock terms are derived, must remain stable

during tPR.

Figure 4-1. Power-up Reset Waveform

Table 4-1.

Parameter

tPR

VRST

Power-up Reset

Description

Power-up Reset Time

Power-up Reset Voltage

Typ

Max

Units

600

1000

ns

3.8

4.5

V

4 ATF2500C

0777K–PLD–1/24/08

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