ATF2500C(2003) Просмотр технического описания (PDF) - Atmel Corporation
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ATF2500C Datasheet PDF : 20 Pages
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ATF2500C Family
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises
in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable
during tPR.
Parameter
tPR
VRST
Description
Power-up Reset Time
Power-up Reset Voltage
Typ
Max
Units
600
1000
ns
3.8
4.5
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
VIH/VIL
VIH/VIL
VIH/VIL
VIH/VIL
Q Select Pin
State
Low
High
Low
High
Even/Odd
Select
Low
Low
High
High
Even Q1 State
after Cycle
High/Low
X
X
X
Even Q2 State
after Cycle
X
High/Low
X
X
Odd Q1 State
after Cycle
X
X
High/Low
X
Odd Q2 State
after Cycle
X
X
X
High/Low
3
0777I–PLD–4/03
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