ATF1500AS-15AC100 Просмотр технического описания (PDF) - Atmel Corporation

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ATF1500AS-15AC100

High-Performance EE CPLD

Atmel Corporation 

Figure 1. ATF1504AS Macrocell

Programmable Pin-Keeper Option for

Inputs and I/Os

The ATF1504AS offers the option of programming all input

and I/O pins so that pin keeper circuits can be utilized.

When any pin is driven high or low and then subsequently

left floating, it will stay at that previous high or low level.

This circuitry prevents unused input and I/O lines from

floating to intermediate voltage levels, which cause unnec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

by mode when no logic transitions are occurring. This not

only reduces power consumption during inactive periods,

but also provides a proportional power savings for most

applications running at system speeds below 50 MHz. This

feature may be selected as a design option.

I/O Diagram

Input Diagram

Speed/Power Management

The ATF1504AS has several built-in speed and power

management features. The ATF1504AS contains circuitry

that automatically puts the device into a low power stand-

To further reduce power, each ATF1504AS macrocell has

a Reduced Power bit feature. This feature allows individual

macrocells to be configured for maximum power savings.

This feature may be selected as a design option.

All ATF1504ASs also have an optional power down mode.

In this mode, current drops to below 10 mA. When the

power down option is selected, either PD1 or PD2 pins (or

both) can be used to power down the part. The power down

option is selected in the design source file. When enabled,

6

ATF1504ASZ

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