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NT2H0301F0DTL,125

NFC Forum Type 2 Tag compliant IC with 144 bytes user memory and field detection

NXP Semiconductors. 

NXP Semiconductors

NTAG203F

NFC Forum compliant IC with user memory and field detection

7.2.5 Halt state

The halt and idle states constitute the second wait state implemented in the NTAG203F.

An already processed NTAG203F can be set into the halt state using the HALT command.

In the anticollision phase, this state helps the NFC device to distinguish between

processed tags and tags yet to be selected. The NTAG203F can only exit this state on

execution of the WUPA command. Any other data received when the device is in this state

is interpreted as an error and the NTAG203F state is unchanged. Refer to the document

MIFARE collection of currently available application notes for correct implementation of an

anticollision procedure based on the idle and halt states and the REQA and WUPA

commands.

7.3 Data integrity

The following mechanisms are implemented in the contactless communication link

between NFC device and NTAG203F to ensure a reliable data transmission:

• 16 bits CRC per block

• Parity bit for each byte

• Bit count checking

• Bit coding to distinguish between "1", "0", and no information

• Channel monitoring (protocol sequence and bit stream analysis)

7.4 RF interface

The RF-interface is according to the standard for contactless smart cards

ISO/IEC 14443A (see Ref. 1).

The RF-field from the NFC device is always present (with short modulation pulses when

transmitting data), because it is used for the power supply of the tag.

For both directions of data communication there is one start bit at the beginning of each

frame. Each byte is transmitted with a parity bit (odd parity) at the end. The LS Bit of the

byte with the lowest address of the selected block is transmitted first. The maximum frame

length is 164 bits (16 data bytes + 2 CRC bytes = 16 * 9 + 2 * 9 + 1 start bit + 1 end bit).

NTAG203F

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.5 — 28 September 2015

220635

© NXP Semiconductors N.V. 2015. All rights reserved.

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