UPD16326AGB-3B4 Просмотр технического описания (PDF) - NEC => Renesas Technology
Номер в каталоге
Компоненты Описание
производитель
UPD16326AGB-3B4 Datasheet PDF : 12 Pages
| |||
µPD16326A
PIN DESCRIPTION
Pin Symbol
STB
A
B
CLK
BLK
R/L
Pin Name
Latch strobe input
RIGHT data input
LEFT data input
Clock input
Blanking input
Shift control input
O1 to O32
VDD1
VDD2
VSS1
VSS2
High breakdown voltage output
Logic block power supply
Driver block power supply
Logic ground
Driver ground
Pin Number
5
3
10
6
4
8
13 - 44
9
1, 12
5
2, 11
Description
H: Data through L: Data retention
When R/L = H, A: Input B: Output
When R/L = L, A: Output B: Input
Shift is executed on a fall.
H: O1 to O32: ALL “L”
H: Right shift mode A → O1 ... O32 → B
L: Left shift mode B → O32 ... O1 → A
130 V, 20 mA MAX
5 V ±10 %
30 to 130 V
Connected to system GND
Connected to system GND
TRUTH TABLE 1 (SHIFT REGISTER BLOCK)
Input
R/L
CLK
H
↓
H
H or L
L
↓
L
H or L
Output
A
Input
B
OutputNote 1
OutputNote 2
Output
Input
Output
Shift Register
Execution of right shift
Retained
Execution of left shift
Retained
Notes 1. On a clock fall, the data items of S31 are shifted to S32, and output from B.
2. On a clock fall, the data items of S2 are shifted to S1, and output from A.
TRUTH TABLE 2 (LATCH BLOCK)
STB
Operation
L
Retains Sn data immediately before STB becomes L.
H
Outputs shift register data.
TRUTH TABLE 3 (DRIVER BLOCK)
LnNote
×
×
L
H
STB
×
L
H
H
BLK
Driver output state
H
L (all driver outputs: L)
L
Outputs Sn data on STB fall.
L
L
L
H
Note Ln: Latch output
Remark × = H or L, H = high level, L = Low level
3
Share Link: 