M68Z128W
Figure 4. Block Diagram
A
(9)
A
CHIP ENABLE.
DQ
(8)
DQ
CHIP
ENABLE
W
E1
E2
G
ROW
DECODER
MEMORY
ARRAY
VCC
VSS
INPUT
DATA
CTRL
I/O CIRCUITS
COLUMN
DECODER
CHIP ENABLE.
(8)
A
A
AI00665
Table 6. DC Characteristics
(TA = 0 to 70°C; VCC = 3.0V + 0.6V / –0.3V)
Symbol
Parameter
Test Condition
ILI Input Leakage Current
0V ≤ VIN ≤ VCC
ILO Output Leakage Current
0V ≤ VOUT ≤ VCC
ICC1 (1) Supply Current
VCC = 3.6V, (-70)
ICC2 (2) Supply Current (Standby) TTL
VCC = 3.6V, E1 = VIH or
E2 = VIL, f =0
ICC3 (3)
Supply Current (Standby) CMOS
VCC = 3.6V, E1 ≥ VCC – 0.2V
or E2 ≤ 0.2V, f =0
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage
IOH = –1mA
Note: 1. Average AC current, Outputs open, cycling at tAVAV minimum.
2. All other Inputs at VIL ≤ 0.8V or VIH ≥ 2.0V.
3. All other Inputs at VIL ≤ 0.2V or VIH ≥ VCC –0.2V.
Min
–0.5
2
2.4
Typ
Max Unit
±1
µA
±1
µA
20
40
mA
15
300
µA
0.4
15
µA
0.8
V
VCC + 0.5 V
0.4
V
V
4/12