M68Z128WN Просмотр технического описания (PDF) - STMicroelectronics
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M68Z128WN Datasheet PDF : 12 Pages
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M68Z128W
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
VIO (2)
VCC
Storage Temperature
Input or Output Voltage
Supply Voltage
–65 to 150
°C
–0.5 to VCC + 0.5
V
–0.5 to 4.6
V
IO (3)
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Up to a maximum operating VCC of 3.6V only.
3. One output at a time, not to exceed 1 second duration.
Figure 2. TSOP Connections
A11
A9
A8
A13
W
E2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
32
8 M68Z128W 25
9
24
16
17
AI00698B
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
READ MODE
The M68Z128W is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and both Chip Enables (E1 and E2) are as-
serted. This provides access to data from eight of
the 1,048,576 locations in the static memory array,
specified by the 17 address inputs. Valid data will
be available at the eight output pins within tAVQV
after the last stable address, providing G is Low,
E1 is Low and E2 is High. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (tE1LQV,
tE2HQV, or tGLQV) rather than the address. Data out
may be indeterminate at tE1LQX, tE2HQX and tGLQX,
but data lines will always be valid at tAVQV.
WRITE MODE
The M68Z128W is in the Write mode whenever
the W and E1 pins are Low, with E2 High. Either
the Chip Enable inputs (E1 and E2) or the Write
Enable input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of both Chip
Enables being active with W low. Therefore, ad-
dress setup time is referenced to Write Enable and
both Chip Enables as tAVWL, tAVE1L and tAVE2H re-
spectively, and is determined by the latter occur-
ring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, W, or the falling edge of E2.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVE1H be-
fore the rising edge of E1 or for tDVE2L before the
falling edge of E2, whichever occurs first, and re-
main valid for tWHDX, tE1HDX or tE2LDX.
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