AD781 Просмотр технического описания (PDF) - Analog Devices

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AD781

Complete 700 ns Sample-and-Hold Amplifier

Analog Devices 

AD781

DYNAMIC PERFORMANCE

The AD781 is compatible with 12-bit A-to-D converters in

terms of both accuracy and speed. The fast acquisition time, fast

hold settling time and good output drive capability allow the

AD781 to be used with high speed, high resolution A-to-D

converters like the AD674 and AD7672. The AD781’s fast

acquisition time provides high throughput rates for multichannel

data acquisition systems. Typically, the sample and hold can

acquire a 10 V step in less than 600 ns. Figure 1 shows the

settling accuracy as a function of acquisition time.

0.08

0.06

(VOUT HOLD – VIN ), mV

+1

–5 –4 –3 –2 –1

VIN , VOLTS

1 2 3 4 +5

GAIN ERROR

HOLD MODE OFFSET

–1

NONLINEARITY

0.04

0.02

0

0

250

500

750

1000

ACQUISITION TIME – ns

Figure 1. VOUT Settling vs. Acquisition Time

The hold settling determines the required time, after the hold

command is given, for the output to settle to its final specified

accuracy. The typical settling behavior of the AD781 is shown

in Figure 2. The settling time of the AD781 is sufficiently fast to

allow the SHA, in most cases, to directly drive an A-to-D

converter without the need for an added “start convert” delay.

Figure 3. Hold Mode Offset, Gain Error and Nonlinearity

For applications where it is important to obtain zero offset, the

hold mode offset may be nulled externally at the input to the

A-to-D converter. Adjustment of the offset may be accom-

plished through the A-to-D itself or by an external amplifier

with offset nulling capability (e.g., AD711). The offset will

change less than 0.5 mV over the specified temperature range.

SUPPLY DECOUPLING AND GROUNDING

CONSIDERATIONS

As with any high speed, high resolution data acquisition system,

the power supplies should be well regulated and free from exces-

sive high frequency noise (ripple). The supply connection to the

AD781 should also be capable of delivering transient currents to

the device. To achieve the specified accuracy and dynamic per-

formance, decoupling capacitors must be placed directly at both

the positive and negative supply pins to common. Ceramic type

0.1 µF capacitors should be connected from VCC and VEE to

common.

ANALOG

P.S.

+12V

C –12V

DIGITAL

P.S.

C +5V

0.1µF 0.1µF

1µF 1µF

1µF

Figure 2. Typical AD781 Hold Mode

HOLD MODE OFFSET

The dc accuracy of the AD781 is determined primarily by the

hold mode offset. The hold mode offset refers to the difference

between the final held output voltage and the input signal at the

time the hold command is given. The hold mode offset arises

from a voltage error introduced onto the hold capacitor by

charge injection of the internal switches. The nominal hold

mode offset is specified for a 0 V input condition. Over the

input range of –5 V to +5 V, the AD781 is also characterized for

an effective gain error and nonlinearity of the held value, as

shown in Figure 3. As indicated by the AD781 specifications,

the hold mode offset is very stable over temperature.

INPUTS

AD781

+

7

9

11 15 1

DIGITAL

AD674

DATA

OUTPUT

SIGNAL GROUND

Figure 4. Basic Grounding and Decoupling Diagram

The AD781 does not provide separate analog and digital ground

leads as is the case with most A-to-D converters. The common

pin is the single ground terminal for the device. It is the refer-

ence point for the sampled input voltage and the held output

voltage and also the digital ground return path. The common

pin should be connected to the reference (analog) ground of the

A-to-D converter with a separate ground lead. Since the analog

and digital grounds in the AD781 are connected internally, the

–6–

REV. A

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