MX589P Просмотр технического описания (PDF) - MX-COM Inc

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MX589P

High Speed GMSK Modem

MX-COM Inc  

High Speed GMSK Modem 4k to 64kbps

9

MX589

PLLacq

1

Rx HOLD

1

1 to 0

1

0

1

0

0

RxDCacq Rx HOLD

0 to 1

X

1

X

0

1

0

0

X = Do not care

Acquire

Medium Bandwidth

Narrow Bandwidth

Hold

Clamp

Fast Peak Detect

Averaging Peak Detect

Hold

PLL Action

Sets the PLL bandwidth wide enough to allow a lock to the received

signal in less than 8 zero crossings. This mode will operate as long

as PLLacq is a logic “1”.

The correction applied to the extracted clock is limited to a

maximum of ±1/16th bit-period for every two received zero-

crossings. The PLL operates in this mode for a period of about 30

bits immediately following a 1 to 0 transition of the PLLacq input,

provided that the Rx HOLD input is a logic 1.

The correction applied to the extracted clock is limited to a

maximum of ±1/64th bit-period for every two received zero-

crossings. The PLL operates in this mode whenever the Rx HOLD

Input is a logic 1 and PLLacq has been a logic 0 for at least 30 bit

periods (after Medium Bandwidth operation for instance).

The PLL feedback loop is broken, allowing the RX Clock to

freewheel during signal fade periods.

Rx Level Measure Action

Operates for one bit-time after a 0 to 1 transition of the RXDCacq

input. The external capacitors are rapidly charged towards a

voltage mid-way between the received signal input level and VBIAS,

with the charge time-constant being of the order of 0.5bit-time.

The voltage detectors act as peak-detectors, one capacitor is used

to capture the positive-going signal peaks of the RX Filter output

signal and the other capturing the negative-going peaks. The

detectors operate in this mode whenever the RXDCacq input is at a

logic 1, except for the initial 1-bit Clamp-mode time.

Provides a slower but more accurate measurement of the signal

peak amplitudes.

The capacitor charging circuits are disabled so that the outputs of

the voltage detectors remain substantially at the last readings

(discharging very slowly [time-constant approx. 2,000 bits] towards

VBIAS).

Table 5: PLL and Rx Level Measurement Operational Modes

4.2.3 Rx Clock Extraction

Synchronized by a PLL circuit to zero-crossings of the incoming data, the Rx Clock Extraction circuitry controls the Rx

Clock output. The Rx Clock is also used internally by the Data Extraction circuitry. The PLL parameters can be varied by

the Rx Circuit Control inputs PLLacq and Rx HOLD to operate in one of four PLL modes as described in Table 5.

4.2.4 Rx Data Extraction

The RX Data Extraction circuit decides whether each received bit is a 1 or 0 by sampling the received signal, after

filtering, and comparing the sample values to an adaptive threshold derived from the Level Measuring circuit. This

threshold is adapted from bit to bit to compensate for intersymbol interference caused by the bandlimiting of the overall

transmission path and the Gaussian premodulation filter. Extracted data is output from the RX Data pin, and should be

sampled externally on the rising edge of the RX CLK.

4.2.5 Rx S/N Detection

The RX S/N Detector system classifies the incoming zero-crossings as GOOD or BAD depending upon the time when

each crossing actually occurs with respect to its expected time as determined by the Clock Extraction PLL. This

information is then processed to provide a logic level output at the RX S/N pin. A high level indicates a series of GOOD

crossings; a low level indicates a BAD crossing.

By averaging this output, it is possible to derive a measure of the Signal-to-Noise-Ratio and hence the Bit-Error-Rate of

the received signal.

©1998 MX-COM, Inc.

www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

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