28C64ASM-3 Просмотр технического описания (PDF) - Turbo IC Inc
Номер в каталоге
Компоненты Описание
производитель
28C64ASM-3 Datasheet PDF : 4 Pages
| |||
Turbo IC, Inc.
28C64A
DEVICE OPERATION
READ:
The 28C64A is accessed like a static RAM. Read operations are initiated
by both CE and OE going low and terminated by either CE or OE return-
ing high. The outputs are at the high impedance state whenever CE or
OE returns high. The two line control architecture gives designers flex-
ibility in preventing bus contention.
WRITE:
A write cycle is initiated when CE and WE are low and OE is high. The
address is latched internally on the falling edge of CE or WE whichever
occurs last. The data is latched by the rising edge of CE or WE whichever
occurs first. Once a byte write cycle has been started, the internal timer
automatically generates the write sequence to the completion of the write
operation.
PAGE WRITE OPERATION:
The page write operation of 28C64A allows one to 64 bytes of data to be
serially loaded into the device and then simultaneously written into memory
during the internally generated write cycle. After the first byte has been
loaded, successive bytes of data may be loaded until the full page of 64
bytes is loaded. Each new byte to be written must be loaded within 200
µs of the previously loaded byte. The page address defined by the ad-
dresses A6-A12 is latched by the first CE or WE falling edge which ini-
tiates a writing cycle and they will stay latched until the completion of the
page write. Any changes in the page addresses during the load-write
cycle will not affect the initially latched page addresses. Addresses A0 -
A5 are used to define which bytes will be loaded and written within the 64
bytes page. The bytes may be loaded in any order that is convenient to
the user. The content of a loaded byte may be altered at any time during
the loading cycle if the maximum allowed byte-load time (200 µs) is not
exceeded. Only loaded bytes within the page will be written; no rewriting
will occur to the non-selected bytes in the page.
DATA POLLING:
The 28C64A features DATA POLLING to indicate the completion of a
write cycle to the host system. During a byte or page write cycle, an
attempted read of the last byte loaded into the page will result in the
complement of the loaded byte on all outputs I/O0 - I/O7 (i.e. loaded data
01010110, read data 10101001). Data Polling feature may be used by an
attempted read on one or more outputs (whatever is convenient for the
system developer). Once the write cycle has been completed, true data
is valid on all outputs and the next cycle may be started.
DATA PROTECTION:
The 28C64A has three hardware features to protect the written content
of the memory against inadvertent writes :
a.) Vcc threshold detector: If Vcc is below 2.5 V, the write capa-
bilities of the chip is inhibited for whatever input conditions.
b.) Noise protection: A WE, OE, or CE pulse less than 10 ns in
width is not able to initiate a write cycle.
c.) Write inhibit: Holding OE at low, or CE at high, or WE at high
inhibits the write cycle.
SOFTWARE WRITE PROTECTION:
The 28C64A offers a software controlled data write protection feature. The
device is delivered to the user with the software data write protection DIS-
ABLED; i.e. the device will go to the data write operation as long as Vcc
exceeds 2.5 V and CE, WE, and OE inputs are set at write mode levels.
The 28C64A can be automatically protected against an accidental write
operation during power-up or power-down without any external circuitry by
enabling the software data write protection features. This features is en-
abled after the first write cycle which includes the software algorithm. After
this operation is done, the data write function of the device may be per-
formed only if every page write cycle is preceded by the software algo-
rithm. The device will maintain its software protect feature for the rest of its
life unless that the software algorithm for disabling the protection is imple-
mented.
SOFTWARE ALGORITHM:
The 28C64A has an internal register for the software algorithm which en-
ables the memory to provide the user with additional features:
a.) Software Write Protect Enable
A sequence of three dummy data writes to the memory will activate
internal EEPROM fuses during the first page write cycle. These EE-
PROM fuses will reject any write attempts of new pages of data
unless the three dummy data writes are repeated at the beginning of
any page writes. The timing for the dummy data and addresses must
be the same as for a normal write operation. A violation of the three
steps write protect sequence in data or address timing and content
will abort the procedure and reset the device to the starting point
condition.
Note: After the three dummy data writes, at least one page load/
write cycle must be performed. If no additional page data is added
to the three dummy data writes, the software write protect will
not be enabled until the next write, which will not be protected.
Table 1 shows the required procedure for enabling the software write
protect:
Step
1
2
3
4-67
Mode
Page Write
Page Write
Page Write
Page Write
Address A12-A0
1555 Hex
0AAA Hex
1555 Hex
Address
Data I/O 7-0
AA Hex
55 Hex
A0 Hex
Data
b.) Software Write Protect Disable
The software algorithm of 28C64A includes a six steps sequence of
dummy data writing to disable the software write protect feature de-
scribed in a.). The six steps write sequence shown in Table 2 must
be performed at the beginning of a page write cycle. A violation of
the six steps write sequence in data or address timing and content
will abort the procedure and reset the chip to the starting point con-
dition. After a page write cycle including the six steps write sequence
has been performed, the 28C64A does not require the use of three
dummy data writes described in a.) for the following page write cycle.
The device is at the software write protect disabled state.
Note: After the six dummy data writes, at least one page load/
write cycle must be performed. If no additional page data is added
to the six dummy data writes, the software write protect disable
will not be activated. Table 2 shows the required procedure for dis-
abling the software write protect:
step
1
2
3
4
5
6
7-70
Mode
Page Write
Page Write
Page Write
Page Write
Page Write
Page Write
Page Write
Address A12-A0
1555 Hex
0AAA Hex
1555 Hex
1555 Hex
0AAA Hex
1555 Hex
Address
Data I/O 7-0
AA Hex
55 Hex
80 Hex
AA Hex
55 Hex
20 Hex
Data
c.) Software Chip Clear
The software algorithm of 28C64A includes a sequence of six steps
dummy data writing to perform a chip clear operation. Table 3 shows
the six steps write sequence to perform the software chip clear op-
eration:
Step
1
2
3
4
5
6
Mode
Page Write
Page Write
Page Write
Page Write
Page Write
Page Write
Address A12-A0
1555 Hex
0AAA Hex
1555 Hex
1555 Hex
0AAA Hex
1555 Hex
Data I/O 7-0
AA Hex
55 Hex
80 Hex
AA Hex
55 Hex
10 Hex
At the end of the six steps write sequence shown in Table 3, the
device automatically activates its internal timer to control the chip
Share Link: 