M48T129V Просмотр технического описания (PDF) - STMicroelectronics
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M48T129V Datasheet PDF : 22 Pages
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M48T129Y, M48T129V
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C)
M48T129Y
M48T129V
Symbol
Parameter
-70
-85
Min
Max
Min
Max
tAVAV Write Cycle Time
70
85
tAVWL Address Valid to Write Enable Low
0
0
tAVEL Address Valid to Chip Enable Low
0
0
tWLWH Write Enable Pulse Width
50
60
tELEH Chip Enable Low to Chip Enable High
55
65
tWHAX Write Enable High to Address Transition
5
5
tEHAX Chip Enable High to Address Transition
10
15
tDVWH Input Valid to Write Enable High
30
35
tDVEH Input Valid to Chip Enable High
30
35
tWHDX Write Enable High to Input Transition
5
5
tEHDX Chip Enable High to Input Transition
10
15
tWLQZ (1, 2) Write Enable Low to Output Hi-Z
25
30
tAVWH Address Valid to Write Enable High
60
70
tAVEH Address Valid to Chip Enable High
60
70
tWHQX (1, 2) Write Enable High to Output Transition
5
5
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
1FFF7h. Bits BMB4-BMB0 store a binary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T129Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FFF0h). The
most significant bit of the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a ’0’,
the watchdog will activate the IRQ/FT pin when
timed-out. When WDS is set to a ’1’, the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT bit
will reset to a ’0’ at the end of a Watchdog time-out
when the WDS bit is set to a ’1’. The watchdog tim-
er can be reset by having the original time-out pe-
riod re-written into the Watchdog Register,
effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
1FFF0h). The watchdog function is automatically
disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set
to output to the IRQ/FT pin and the frequency test
function is activated, the watchdog or alarm func-
tion prevails and the frequency test function is de-
nied.
10/22
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