MT5C1005 Просмотр технического описания (PDF) - Unspecified

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производитель

MT5C1005

256K x 4 SRAM SRAM MEMORY ARRAY

Unspecified 

Austin Semiconductor, Inc.

SRAM

MT5C1005

WRITE CYCLE NO. 1 12

(Chip Enabled Controlled)

ADDRESS

ttAASS

CE\

WE\ 1122334455667788990011223344556677889900111122

ttWWCC

ttAAWW

ttCCWW

ttWWPP1

ttDDSS

ttAAHH

112233445566778899001122334455667788990011223344556677889900112211223344556677889900

ttDDH

D

DATA VAILD

Q

HIGH Z

ADDRESS

CE\ 11122233344455566677788899900011122233344455566677111722211

WRITE CYCLE NO. 2 7, 12

(Write Enabled Controlled)

ttWWCC

ttAAWW

ttCCWW

ttAAHH

12111222333444555666777888999000111222333444555666777888999000111222333

tAS tAS

WE\

D

ttWWPP1

tDS

ttDDHH

DATA VALID

Q

HIGH-Z

NOTE: Output enable (OE\) is inactive (HIGH).

111111112222222233333333444444445555UDNODNE’TFCINAERDE

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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