AS5SS256K18 Просмотр технического описания (PDF) - Austin Semiconductor
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AS5SS256K18 Datasheet PDF : 13 Pages
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Austin Semiconductor, Inc.
SSRAM
AS5SS256K18
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS............-0.5V to +4.6V
Voltage on VDDQ Supply Relative to VSS.........-0.5V to +4.6V
Storage Temperature (plastic) .....................-55°C to +125°C
Max Junction Temperature**.......................................+150°C
Short Circuit Output Current..........…...........................100mA
*Stresses greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
**Maximum junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC and -40oC<TA<+85oC; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
CONDITIONS
(0V<VIN<VDD)
Output(s) disabled;
0V<VIN<VDD
IOH = -4.0mA
IOL = 8.0 mA
SYMBOL
VIH
VIL
ILI
ILO
VOH
VOL
VDD
VDDQ
MIN
2.0
-0.3
-2
-2
2.4
--
3.135
3.135
MAX
VDD +0.3
0.8
2
2
--
0.5
3.6
3.6
UNITS
V
V
µΑ
µΑ
V
V
V
V
NOTES
1, 2
1, 2
3
1, 4
1, 4
1
1, 5
CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CONDITIONS
TA = 25°C; f = 1MHz;
VDD = 3.3V
SYM
CI
CO
CA
CCK
MAX
4
5
3.5
3.5
UNITS
pF
pF
pF
pF
NOTES
6
6
6
6
THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
SYM
θJA
θJC
TYP UNITS NOTES
46
°C/W
6
2.8
°C/W
6
NOTES:
1. All voltages referenced to VSS (GND)
2. Overshoot: VIH < +4.6V for t < tKC/2 for I < 20mA
Undershoot: VIL > -0.7V for t < tKC/2 for I < 20mA
Power-up: V < +3.6V and V <3.135V for t < 200ms
IH
DD
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for V , V testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values.
OH OL
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.
6. This parameter is sampled.
AS5SS256K18
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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