M82510 Просмотр технического описания (PDF) - Intel

Номер в каталоге

Компоненты Описание

производитель

M82510

ASYNCHRONOUS SERIAL CONTROLLER

Intel 

M82510

Figure 4 Interrupt Structure

271072 – 4

Interrupts

There are two levels of interrupt status reporting

within the M82510 The first level is the block level

interrupts such as RX FIFO Tx FIFO Rx Machine

Tx Machine Timing unit and Modem Module The

status of these blocks is reported in the General

Status and General Interrupt Registers The second

level is the various sources within each block only

three of the blocks generate second level interrupts

(Rx Machine Timing Unit and Modem Module) In-

terrupt requests are maskable at both the block level

and at the individual source level within the module

If more than one unmasked block requests interrupt

service an on-chip interrupt controller will resolve

contention on a priority basis (each block has a fixed

priority) An interrupt request from a particular block

is activated if one of the unmasked status bits within

the status register for the block is set A CPU service

operation e g reading the appropriate status regis-

ter will reset the status bits

ACKNOWLEDGE MODES

The interrupt logic will assert the INT pin when an

interrupt is coded into the General Interrupt register

The INT pin is forced low upon acknowledgment

The M82510 has two modes of interrupt acknowl-

edgment

1 Manual Acknowledge

The CPU must issue an explicit Interrupt Acknowl-

edge command via the Interrupt Acknowledge bit of

the Internal Command register As a result the INT

pin is forced low for two clocks and then updated

2 Automatic Acknowledge

As opposed to the Manual Acknowledge mode

when the CPU must issue an explicit interrupt ac-

knowledge command an interrupt service operation

is considered as an automatic acknowledgment

This forces the INT pin low for two clock cycles

After two cycles the INT pin is updated i e if there

is still an active non-masked interrupt request the

INT pin is set HIGH

INTERRUPT SERVICE

A service operation is an operation performed by the

CPU which causes the source of the M82510 inter-

rupt to be reset (it will reset the particular status bit

causing the interrupt) An interrupt request within the

M82510 will not reset until the interrupt source has

been serviced Each source can be serviced in two

or three different ways one general way is to disable

the particular status bit causing the interrupt via the

corresponding block enable register Setting the ap-

propriate bit of the enable register to zero will mask

off the corresponding bit in the status register thus

causing an edge on the input line to the interrupt

logic The same effect can be achieved by masking

6

Share Link: