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AD1878

High Performance 16-/18-Bit ΣΔ Stereo ADCs

Analog Devices 

AD1878/AD1879

Sample Delay

The sample delay or “group delay” of the AD1878/AD1879 is

dominated by the processing time of the digital decimation fil-

ter. FIR filters convolve a vector representing time samples of

the input with an equal-sized vector of coefficients. After each

convolution, the input vector is updated by adding a new

sample at one end of the “pipeline” and eliminating the oldest

input sample at the other. For an FIR filter, the time at which a

step input appears at the output will be approximately when that

step input is halfway through the input sample vector pipeline.

The input sample vector is updated every 64 × FS. Thus, the

sample delay will be given by the equation,

Group Delay = (4096Ϭ 2) /(64 × FS) = 32 / FS

For the most common sample rates this can be summarized as:

FS

48 kHz

44.1 kHz

32 kHz

Group Delay

667 µs

725 µs

1000 µs

Due to the linear phase properties of FIR filters, the group delay

variation, or differences in group delay at different frequencies is

zero.

OPERATING FEATURES

Voltage Reference

The AD1878/AD1879 includes a +3 V on-board reference

which determines the AD1878/AD1879’s input range. This ref-

erence is buffered to both channels of the AD1878/AD1879’s

modulator, providing a well-matched reference to minimize

interchannel gain mismatch. The reference should be bypassed

with 10 µF tantalum capacitors as shown in Figure 2. The inter-

nal reference can be overpowered by applying an external refer-

ence at the REFR (Pin 14) and REFL (Pin 15) pins, allowing

multiple AD1878/AD1879s to be calibrated to the same gain.

Note that the reference pins still must be bypassed as shown.

Sample Clock

An external master clock supplied to CLOCK (Pin 26) drives

the AD1878/AD1879 modulator, decimator, and digital inter-

face. As with any analog-to-digital conversion system, the sam-

pling clock must be low jitter to prevent conversion errors.

The input clock operates at 256 × FS. The clock is divided down

to obtain the 64 × FS clock required for the modulator. The out-

put word rate will be at FS itself. This relationship is illustrated

for popular sample rates below:

AD1879

CLOCK Input

12.288 MHz

11.2896 MHz

8.192 MHz

Modulator

Sample Rate

3.072 MHz

2.822 MHz

2.048 MHz

Output Word

Rate

48 kHz

44.1 kHz

32 kHz

The AD1878/AD1879 serial interface supports both “master”

and “slave” modes. Note that even in slave mode it is presumed

that the serial interface clocks are derived from the master clock

input, CLOCK. Slave mode does not support asynchronous

data transfers, since asynchronous data transfers would compro-

mise the performance of any high performance converter.

The AD1878/AD1879 decimator makes use of dynamic logic to

minimize die area. There is, therefore, a minimum clock fre-

quency that the AD1878/AD1879 will support specified in

“Specifications” above. Operation of the AD1878/AD1879 at

lower frequencies will cause the device to consume excessive

power and may damage the converter.

Reset

The active LO RESET pin (Pin 24) allows initializing the

AD1879. This is of value only for synchronizing multiple

AD1878/AD1879s in Master Mode—WCK Output. Unless you

are interested in synchronizing multiple AD1878/AD1879s, we

recommend tying RESET HI. The reset function is useful for

nothing else. In fact, there is a maximum specification on

RESET LO; excessive power consumption may occur with loss

of reliability if left LO too long due to the dynamic logic on the

chip.

Figure 14 illustrates the timing parameters for RESET to

accomplish synchronization of multiple Master Mode—Word

Clock Output ADCs. (This sequence is not necessary for syn-

chronizing multiple AD1878/AD1879s in other modes. See

“Synchronizing Multiple AD1878/AD1879s” below.) Note that

RESET first has to be LO for at least four CLOCK periods

(three CLOCKs plus tRSET plus tRHLD, to be more precise).

Then RESET must be HI for a minimum of one CLOCK and a

maximum of two CLOCKs. Then RESET must he LO for at

least another four CLOCKs. From the time when RESET goes

HI again, exactly 127 CLOCKs will occur before LRCK goes

LO.

Analog Power Down

The AD1878/AD1879 features a power-down mode that

reduces current to the analog modulator. It is controlled by

the active HI APD (Pin 11). The power savings are specified in

“Specifications.” The converter is still “alive” in the power-

down state but will not produce valid results for all audio-band

inputs.

Power consumption can be further reduced by slowing down

the master clock input to the minimum clock frequency,

FCLOCK, specified for the AD1878/AD1879.

APPLICATIONS ISSUES

Recommended Input Structure

The AD1878/AD1879 input structure is fully differential for

improved common-mode rejection properties and increased

dynamic range. Since each input pin sees ± 3 V swings, each

channel’s input signal effectively swings ± 6 V, i.e., across a

12 V range.

In most cases, a single-ended-to-differential input circuit is

required. Shown in Figure 2 is our recommended circuit, based

on extensive experimentation. Note that to maximize signal

swing, the op amps in this circuit are powered by ± 12 V or

greater supplies. The AD1878/AD1879 itself requires ± 5 V

supplies. If ± 5 V supplies are not already available in your sys-

tem, Figure 3 illustrates our recommended circuit for generat-

ing these supplies.

REV. 0

–7–

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