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ADP1147AR-3.3

High Efficiency Step-Down Switching Regulator Controllers

Analog Devices 

ADP1147-3.3/ADP1147-5

To obtain optimum efficiency the required ESR value of COUT

is 100 mΩ or less.

The circuit should also be evaluated with the minimum input

voltage. This is done to assure that the power dissipation and

junction temperature of the P-channel MOSFET are not ex-

ceeded. At lower input voltages the operating frequency of the

ADP1147 decreases. This causes the P-channel MOSFET to

remain in conduction for longer periods of time, resulting in

more power dissipation in the MOSFET.

The effects of VIN(MIN) can be evaluated if we assume the

following:

VIN(MIN) = 4.5 V

VOUT = 3.3 V

VD = 0.4 V

fMIN = (1/3.15 µs) × (1– (3.7/4.9)) = 78 kHz.

PD

=

3.3 (0.125

Ω)(1 A)2

4.5

(1.2625 )

= 116

mW

Troubleshooting Hints

Efficiency is the primary reason for choosing the ADP1147 for

use in an application, and it is critical to determine that all por-

tions of the circuit are functioning properly in all modes. After

the design is complete the voltage waveforms on the timing

capacitor, CT, at Pin 2 of the device, should be compared to the

waveforms in Figures 19a and 19b.

In the continuous mode of operation the dc voltage level of the

waveform on CT should never fall below the 2 V level and it

should have a 0.9 V peak-to-peak sawtooth on it (see Figure

19a).

In the Power Savings Mode the sawtooth waveform on CT will

decay to ground for extended periods of time (see Figure 19b).

During the time that the capacitor voltage is at ground the

ADP1147 is in the power savings or sleep mode and the qui-

escent current is reduced to 160 µA typical.

The ripple current in the inductor should also be monitored to

determine that it is approximately the same in both modes of

operation. With a higher output currents the voltage level on CT

should never decay to ground as this would indicate poor

grounding and or decoupling.

Printed Wire Board Layout Considerations

The PWB layout is extremely critical for proper circuit opera-

tion and the items listed below should be carefully considered

(see Figure 20)

1. The signal and power grounds should be separate from each

other. They should be tied together only at ground Pin 7 of

the ADP1147. The power ground should be tied to the an-

ode of the Schottky diode, and the (–) side of the CIN capaci-

tor. The connections should be made with traces that are as

wide and as short as possible. The signal ground should be

connected to the (–) side of capacitor COUT using the same

type of runs as above.

2. The sense(–) run to Pin 4 of the ADP1147 should be con-

nected directly to the junction point of RSENSE and the + side

of COUT.

3. The sense(–) and sense(+) traces should be routed together

with minimum track spacing and run lengths. The 1000 pF

filter capacitor across Pins 4 and 5 of the ADP1147 should

be located as close to the device as possible.

4. In order to supply sufficient ac current the (+) side of capaci-

tor CIN should be connected with wide short traces and must

be located as close to the source of the P-MOSFET as possible.

5. In order to supply high frequency peak currents the input

decoupling capacitors should range from 0.1 µF to 1.0 µF

and must be located as close to the VIN pin and the ground

Pin 7 as possible.

6. The shutdown Pin (6) is a high impedance input and it must

not be allowed to float. The normal mode of operation of the

device requires that this pin be pulled low.

REV. 0

–11–

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