ADP3020 Просмотр технического описания (PDF) - Analog Devices

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ADP3020

High-Efficiency Notebook Computer Power Supply Controller

Analog Devices 

ADP3020

PWM Mode/Power-Saving (PSV) Mode Operation

The mode of operation for both switching regulators can be preset

using the MODE pin. When MODE is HIGH, or connected to

INTVCC, both converters work only in PWM mode, regardless

of output current. MODE connected to GND makes both con-

verters operate in a dual PWM/PSV mode of operation. In dual

mode, each converter has its own boundary output current when

the converter switches from PSV mode to PWM mode and vice

versa. There is an output current hysteresis for each mode tran-

sition to avoid improper operation.

There are several design recommendations regarding dual mode

operation. The trip output current level for switching between

PWM mode and PSV mode is a percentage of the peak current

sensed via the internal current sense comparator. However,

the value of that current depends on the RDS(ON) of the upper

MOSFET. For example, if the design uses an Si4420 versus an

Si4410 power MOSFET (9 mΩ vs. 13.5 mΩ) the maximum

output power of the converter and the mode trip output current

will both be 50% higher.

Efficiency Enhancement

The efficiency of each switching regulator is inversely propor-

tional to the losses during the switching conversion. The main

factors to consider when attempting to maximize efficiency are:

1. Resistive losses, which include the RDS(ON) of upper and

lower MOSFETs, trace resistances and output choke wire

resistance.

These losses contribute a major part of the overall power loss

in low voltage battery-powered applications. However, trying

to reduce these resistive losses by using multiple MOSFETs

and thick traces may tend to lead to lower efficiency and higher

price. This is due to the trade-off between reduced resistive

loss and increased gate drive loss that must be considered

when optimizing efficiency.

2. Switching losses due to the limited time of switching transitions.

This occurs due to gate drive losses of both upper and lower

MOSFETs, and switching node capacitive losses, as well as

through hysteresis and eddy-current losses in power choke.

Input and output capacitor ripple current losses should also

be considered as switching losses. These losses are input-

voltage-dependent and can be estimated as follows:

PSWLOSS = 2.5 × VIN1.85 × IMAX × CSN × f

(17)

where CSN is the overall capacitance of the switching node

related to loss.

3. Supply current of the switching controller (independent of

the input current redirected to supply the MOSFETs’ gates).

This is a very small portion of the overall loss, but it does

increase with input voltage.

Transient Response Considerations

Both stability and regulator loop response can be checked by

looking at the load transient response. Switching regulators take

several cycles to respond to a step in output load current. When

a load step occurs, output voltage shifts by an amount equal to

the current step multiplied by the total ESR of the summed output

capacitor array. Output overshoot or ringing during the recovery

time (in both directions of the current step change) indicates a

stability problem. The external feedback compensation compo-

nents shown in Figure 18 should provide adequate

compensation for most applications.

Feedback Loop Compensation

The ADP3020 uses Voltage Mode control to stabilize the switch-

ing controller outputs. Figure 20 shows the voltage mode control

loop for one of the buck switching regulators. The internal refer-

ence voltage VREF is applied to the positive input of the internal

error amplifier. The other input of the error amplifier is EAN,

and is internally connected to the feedback sensing pin FB via an

internal resistor. The error amplifier creates the closed-loop

voltage level for the pulsewidth modulator that drives the external

power MOSFETs. The output LC filter smooths the pulse-

width modulated input voltage to a dc output voltage.

PWM

COMPARATOR

VRAMP

ADP3020

DRVH

DRVL

EAO

EAN

R1

REF FB

VIN

L1

VOUT

COUT

C2

C1 R2

PARASITIC

ESR

C3

R3

Figure 20. Buck Regulator Voltage Control Loop

The pulsewidth modulator transfer function is VOUT/VEAOUT,

where VEAOUT is the output voltage of the error amplifier. That

function is dominated by the impedance of the output filter with

its double-pole resonance frequency (fLC) and a single zero at

output capacitor (fESR) and the dc gain of the modulator, equal

to the input voltage divided by the peak ramp height (VRAMP),

which is equal to VREF (1.2 V):

fLC =

1

2 π × LF × COUT

(18)

FESR

=

2π

×

1

ESR

× COUT

(19)

REV. 0

–17–

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