X24645S8I Просмотр технического описания (PDF) - IC MICROSYSTEMS

Номер в каталоге

Компоненты Описание

производитель

X24645S8I

Advanced 2-Wire Serial E2PROM with Block Lock™ Protection

IC MICROSYSTEMS 

X24645

DEVICE ADDRESSING

Following a start condition the master must output the

address of the slave it is accessing (see Figure 4). The

next two bits are the device select bits. A system could have

up to four X24645’s on the bus. The four

addresses are defined by the state of the S1 and S2 inputs.

S2 of the slave address must be the inverse of

the S2 input pin.

Figure 4. Slave Address

The last bit of the slave address defines the operation to be

performed. When set HIGH a read operation is

selected, when set LOW, a write operation is selected.

Following the start condition, the X24645 monitors the SDA

bus comparing the slave address being transmitted

with its slave address device type identifier. Upon a

correct compare the X24645 outputs an acknowledge on

the SDA line. Depending on the state of the R/W bit, the

X24645 will execute a read or write operation.

DEVICE

SELECT

HIGH ORDER

ADDRESS

BITS

S

2

S

1

A12 A11 A10 A9 A8 R/W

2783 ILL F07.1

The next five bits of the slave address are an extension of

the array’s address and are concatenated with

the eight bits of address in the byte address field,

providing direct access to the whole 8192 x 8 array.

WRITE OPERATIONS

Byte Write

For a write operation, the X24645 requires a second ad-

dress field. This address field is the byte address, com-

prised of eight bits, providing access to any one of 8192

words in the array. Upon receipt of the byte address, the

X24645 responds with an acknowledge and awaits the

next eight bits of data, again responding with an acknowledge

The master then terminates the transfer by generating a

stop condition, at which time the X24645 begins

the internal write cycle to the nonvolatile memory. While the

internal write cycle is in progress the X24645 inputs

are disabled, and the device will not respond to any requests

from the master. Refer to Figure 5 for the address,

acknowledge and data transfer sequence.

Figure 5. Byte Write

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24645

S

T

SLAVE

A ADDRESS

R

T

S

BYTE

ADDRESS

A

A

C

C

K

K

S

DATA

T

O

P

P

A

C

K

2783 ILL F08.1

5

Share Link: