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T14L256A Просмотр технического описания (PDF) - Taiwan Memory Technology

Номер в каталоге
Компоненты Описание
производитель
T14L256A
TMT
Taiwan Memory Technology TMT
T14L256A Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
tm TE
CH
T14L256A
AC CHARACTERISTICS
(Vcc=3.3V ± 5%, Vss = 0V, Ta = 0 to 70°C)
(1) READ CYCLE
PARAMETER
Read Cycle Time
SYM. T14L256A-8 T14L256A-10 T14L256A-12 T14L256A-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tRC 8 - 10 - 12 - 15 - ns
Address Access Time
tAA - 8 - 10 - 12 - 15 ns
Chip Select Access Time
tACS -
8
-
10
-
12
- 15 ns
Output Enable to Output Valid
tAOE -
5
-
6
-
7
- 7 ns
Chip Selection to Output in Low Z tCLZ* 3 - 3
-
3
-
3 - ns
Output Enable to Output in Low Z tOLZ 0 - 0
-
0
-
0 - ns
Chip Deselection to Output in High Z tCHZ* - 4 -
5
-
6
0 7 ns
Output Disable to Output in High Z tOHZ - 4 -
5
-
6
0 7 ns
Output Hold from Address Change tOH 2.5 - 3
-
3
-
3 - ns
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
PARAMETER
Write Cycle Time
SYM. T14L256A-8 T14L256A-10 T14L256A-12 T14L256A-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tWC 8 - 10 - 12 - 15 - ns
Chip Selection to End of Write tCW 6 -
8
- 10 - 11 - ns
Address Valid to End of Write
tAW 6
-
8
- 10 - 11 - ns
Address Setup Time
tAS
0
-
0
-
0
-
0
- ns
Write Pulse Width
tWP
6
-
8
- 10 - 11 - ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
- ns
Data Valid to End of Write
tDW 5
-
6
-
8
-
8
- ns
Data Hold from End of Write
tDH
0
-
0
-
0
-
0
- ns
Write to Output in High Z
tWHZ -
4
-
5
-
6
-
6 ns
Output Disable to Output in High Z tOHZ - 4
-
5
-
6
-
7 ns
Output Active from End of Write tOW 0 -
0
-
0
-
0
- ns
* These parameters are sampled but not 100% tested.
TM Technology Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: NOV. 2003
Revision: F

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