SP8855D Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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производитель

SP8855D

1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER

Zarlink Semiconductor Inc 

SP8855D

+5V

V CC

* VALUES DEPEND

ON APPLICATION

RF COUNTER

PROGRAMMING

1k

VCO

1n

APPLICATION USING

CRYSTAL REFERENCE

SP8855

27

28

33p

1n

100p

10MHz

CRYSTAL

7

8

9

10

11

12

13

14

15

16

17

2k2

10n

SP8855D

Fpd Fref

* 100p

1m 10n

REFERENCE COUNTER

PROGRAMMING

V CC

39

38

37

36

35

34

33

32

31

LOOP

30

FILTER

29

*

*

*

+30V

–

+ OP27

ETC

100n

1n

Fig. 5 Typical application diagram

Ref in

DESCRIPTION

Prescaler and AM counter

The programmable divider chain is of A M counter

construction and therefore contains a dual modulus front end

prescaler, an A counter which controls the dual modulus ratio

and an M counter which performs the bulk multi–modulus

division. A programmable divider of this construction has a

division ratio of MN+A and a minimum integer steppable

division ratio of N(N–1), where N is the prescaler ratio.

Programming

The device is programmed by connecting the programming

pins to either VCC or ground. The programming inputs will go

high if left open circuit but for best noise immunity a wired

connection to VCC is preferable. The programming inputs can

be driven from TTL or CMOS logic levels if required.

Reference input

The reference source can be either driven from an external

sine or square wave source of up to 100MHz or a crystal can

be connected as shown in Fig. 5.

Phase Comparator and Charge pump

The SP8855D has a digital phase/frequency comparator

driving a charge pump with programmable current output. The

charge pump current level at the minimum gain setting is

approximately equal to the current fed into the Rset input pin

19 and can be increased by programming pins 40 and 41

according to Table 1 by up to 4 times.

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