SP8855D Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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SP8855D

1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER

Zarlink Semiconductor Inc 

PIN DESCRIPTION

PIN

1,2,3,4,5,6,7,8,9,10,11,42,43,44

13, 14 (RF INPUT)

17 (LOCK DETECT INPUT)

18 (C–LOCK DETECT)

19 (Rset)

20 (CP OUTPUT)

21 (CP REF)

22 (Fref/Fpd ENABLE)

23 (CONTROL DIRECTION)

24 =Fpd if Pin 23 is HI

=Fref if Pin 23 is LO

25 =Fref if Pin 23 is HI

=Fpd if pin 23 is LO

27 (Reference Oscillator Capacitor)

28 (Ref IN/XTAL)

29,30,31,32,33,34,35,36,37,38

39 (Phase Detector ENABLE)

40, 41 (PD Gain)

SP8855D

DESCRIPTION

These pins are the data inputs used to set the RF divider ratio (M.N+A). Open

circuit=1 (high) on these pins. Inputs are transparent into the data buffers.

Balanced inputs to the RF pre–amplifier. For single ended operation the signal is

AC coupled into pin 13 with pin 14 AC decoupled to ground (or vice–versa.) Pins

13 and 14 are internally DC biased.

A current sink into this pin is enabled when the lock detect circuit indicates lock.

Used to give an external indication of phase lock.

A capacitor connected to this point determines the lock detect integrator time

constant and can be used to vary the sensitivity of the phase lock indicator.

An external resistor from Pin 19 to VCC sets the charge pump output current.

The phase detector output is a single ended charge pump sourcing or sinking

current to the inverting input of an external loop filter.

Connected to the non–inverting input of the loop filter to set the optimum DC bias.

Part of the data input bus. When this pin is logic HI the Fref and Fpd outputs are

enabled. Open circuit=HI.

This pin controls charge pump output direction. For Pin 23 HI the output sinks

current when Fpd > Fref or when the RF phase leads Ref phase. For Pin 23 LO the

relationship is reversed. (see table 2).

Changing the state of pin 23 reverses the pins on which Fref and Fpd output occur.

See pin 24 and Pin 25 below for details. Open circuit =HI.

RF divider output pulses. Fpd=RF input frequency/(M.N+A). Pulse width=8

RF input cycles (1 cycle of the divide by 8 prescaler output).

Reference divider output pulses. Fref=Reference input frequency/R. Pulse width

=high period of Ref input.

Leave open circuit if an external reference is used. See Fig. 5 for typical

connection for use as an onboard crystal oscillator.

This pin is the input buffer amplifier for an external reference signal. This amplifier

provides the active element if an onboard crystal oscillator is used.

These pins set the Reference divider ratio R. Open circuit =HI.

When this pin is HI the phase detector output is enabled. Open circuit =HI.

These pins set the charge pump current multiplication factor (see table 1). Open

circuit =HI.

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