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ST20-GP6

GPS PROCESSOR

STMicroelectronics 

ST20-GP6

The ST20-GP6 can use 8 or 16-bit external RAM, 8 or 16-bit external ROM, and has a 20-bit

address bus.

The ST20-GP6 product has 64 Kbytes of on-chip SRAM. This is in 4 banks of 16 Kbytes. One of

these banks is powered from the back-up battery supply. The ST20-GP6 has 128 Kbytes of ROM

for application code.

The ST20-GP6 memory interface controls the movement of data between the ST20-GP6 and off-

chip memory. It is designed to support memory subsystems without any external support logic and

is programmable to support a wide range of memory types. Memory is divided into 4 banks which

can each have different memory characteristics and each bank can access up to 1 Mbyte of

external memory.

The normal memory provision in a simple GPS receiver is a single 64K x 16-bit ROM or Flash

ROM (70, 90 or 100 ns access time). The internal 64 Kbyte RAM is sufficient for application use,

however for development purposes external RAM may be added. The ST20-GP6 can support up to

1 Mbyte of SRAM plus 1 Mbyte of ROM, enabling additional functions to be added if required.

Low power controller, real time clock and watchdog timer

The ST20-GP6 has power-down capabilities configurable in software. When powered down, a

timer can be used as an alarm, re-activating the CPU after a programmed delay. This is suitable for

ultra low power or solar powered applications such as container tracking, railway truck tracking, or

marine navigation buoys that must check they are on station at intervals.

There is also a watchdog timer (WDT), resetting the system if it times out. The watchdog timer

function is enabled by an external pin (WdEnable). The WDT has a counter, clocked to give a

nominal 2 second delay. A status flag (notWdReset) is set by a watchdog reset. This can be used

to indicate to application code that the system was reset by the watchdog timer.

The real time clock (RTC) provides a set of continuously running counters to provide a clock-

calendar function. The counter values can be written to set the current time/data. The RTC is

clocked by a 32,768 Hz crystal oscillator and has a separate power supply so that it can continue to

run when the rest of the chip is powered down.

The RTC contains two counters: a 30-bit ‘milliseconds’ counter and a 16-bit ‘weeks’ counter. This

allows large time values to be represented to high accuracy. Note that the milliseconds counter is

actually clocked at 1.024 KHz and this must be handled by software.

The ST20-GP6 is designed for 0.35 micron, 3.3 V CMOS technology and runs at speeds of up to

50 MHz. 3.3 V operation provides reduced power consumption internally and allows the use of low

power peripherals. In addition, a power-down mode is available on the ST20-GP6.

The different power levels of the ST20-GP6 are listed below.

• Operating power — power consumed during functional operation.

• Stand-by power — power consumed during little or no activity. The CPU is idle but ready to

immediately respond to an interrupt/reschedule.

• Power-down — clocks are stopped and power consumption is significantly reduced. Func-

tional operation is stalled. Normal functional operation can be resumed from previous state

as soon as the clocks are stable. No information is lost during power down as all internal

logic is static.

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