ST20-GP6 Просмотр технического описания (PDF) - STMicroelectronics

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ST20-GP6

GPS PROCESSOR

STMicroelectronics 

ST20-GP6

GPS

radio

12 channel GPS

hardware DSP

Interrupts

Interrupt

controller

Low

power

controller

Real time

clock

Programmable

memory

interface

128K

ROM

64K

SRAM

ST20-GP6

ST20

CPU

Serial

communications

2 UART

Parallel

input/output

... 16

User position

output in

ASCII

Diagnostic

control unit

Test access

port

System

services

Reset

Clock

Figure 2.1 ST20-GP6 architectural block diagram

Memory subsystem

The ST20-GP6 on-chip memory system provides 60 Mbytes/s internal data bandwidth, supporting

pipelined 2-cycle internal memory access at 30 ns cycle times. The ST20-GP6 memory system

consists of SRAM, ROM and a programmable external memory interface (EMI).

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