SDA9401 Просмотр технического описания (PDF) - Unspecified
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SDA9401 Datasheet PDF : 69 Pages
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SDA 9401
Explanation of 656 format
CLK1 (27 MHz)
CCIR 656 interface
YIN
EAV
SAV
u0 y0 v0 y1 u2 y3
EAV
288 Tclk1(PAL)
276 Tclk1(NTSC)
1728 Tclk1(PAL)
1716 Tclk1(NTSC)
CLK1 (27 MHz)
YIN
x
EAV
x
x
SAV
x
x
EAV
x
H656
V656
(e.g.)
F656
(e.g.)
11111111
MSB
LSB
11111111
EAV
00000000
00000000
SAV
00000000
00000000
1FV1P3P2P1P0
1FV0P3P2P1P0
F = 0 during field 1(A)
F = 1 during field 2(B)
V = 0 elsewhere
V = 1 during field blanking
The figure below explains the functionality of the SYNCEN signal. The SDA 9401 needs the
SYNCEN (synchronization enable) signal, which is used to gate the YIN, UVIN as well as the HIN
and the VIN signal. This is implemented for front-ends which are working with 13.5 MHz and a large
output delay time for YIN, UVIN, HIN and VIN (e.g. Micronas VPC32XX, output delay: 35 ns). For
this application the half system clock CLK1 (13.5 MHz) from the front-end should be provided at this
pin. In case the front-end is working at 27.0 MHz with sync signals having delay times smaller than
25 ns, this input can be set to low level (SYNCEN=VSS) (e.g. Micronas SDA 9206, output delay: 25
ns). Thus the signals YIN, UVIN, HIN and VIN are sampled with the CLK1 system clock when the
SYNCEN input is low.
SYNCEN signal
CLK1
SYNCEN
YIN
x
y0
y1
y2
y3
UVIN
x
u0
v0
u2
v2
YINen
x
y0
y1
y2
y3
UVINen
x
u0
v0
u2
v2
HIN/VIN
HINen/VINen
Micronas
14
Preliminary Data Sheet
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