SDT211 Просмотр технического описания (PDF) - Linear Technology

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SDT211

N-CHANNEL LATERAL DMOS SWITCH

Linear Technology 

Since these DMOS devices are asymmetrical1,

the charge injected into the S and D terminals is

different. Typical parasitic capacitances are on

the order of 0.2 pF for CDG and 1.5 pF for CSG.

Another factor that influences the amount of

charge injected is the amplitude of the gate-

voltage excursion. This is a directly

proportional relationship: the larger the

excursion, the larger the injected charge. This

can be seen by comparing curves (a) and (c) in

Figure 9. One other variable to consider is the

rate of gate-voltage change. Large amounts of

charge are injected when faster rise and fall

times are present at the gate. This is shown by

curves (a) and (b) in Figure 9.

S

D

G

CH

∆V

Q = CH x ∆V

0

-2

(c)

(b)

-4

(2)

-6

-8

-10

-10

(a)

(b)

(c)

(a)

(1)

-5

0

5

10

VS (V)

VG = 10 V, tf = 0.3 V/µs

VG = 10 V, tf = 0.03 V/µs

VG = 0, -10 V, tf = 0.3 V/µs

Figure 9. SD5000 Charge Injection

impedance tends to produce a rapid decay of the

extra charge introduced in the channel. At turn-

off, however, the injected charge might become

stored in a sampling capacitor and create offsets

and errors. These errors will have a magnitude

that is inversely proportional to the magnitude

of the holding capacitance.

Figure 9 illustrates several typical charge

injection characteristics. Figure 10 shows some

of the corresponding waveforms. The DMOS

FETs, because of their inherent low parasitic

capacitances, produce very low charge injection

when compared to other analog switches

(PMOS, CMOS, JFET, BIFET etc.). Still, when

the offsets created are unacceptable, charge

injection compensation techniques exist that

eliminate or minimize them. The solution

basically consists of injecting another charge of

equal amplitude but opposite polarity at the time

when the switch turns off.

Off-Isolation and Crosstalk

The dc on-state resistance is typically 30 Ω and

the off-state resistance is typically 1010 Ω,

which results in an off-state to on-state

resistance ratio in excess of 108. However, for

video and VHF switching applications, the

upper usable frequency limit is determined by

how much of the incoming signal is coupled

through the parasitic capacitances and appears at

the switch output─when ideally no signal

should appear there in the off state.

Off-Isolation is defined by the formula:

Switching spikes occur at switch turn-on as well

as turn-off time. When the switch turns on, the

charge injection effect is minimized by the

usually low signal-source impedance. This low

1 The chip geometry is such that non-identical behavior

occurs when the source and drain terminals are reversed

in a circuit.

Off - Isolation (dB) = 20log VOUT

VIN

When several analog switches are

simultaneously being used to control high

frequency signals, crosstalk becomes a very

important characteristic. For video applications,

the stray signal coupled via parasitic

5

Linear Integrated Systems, Inc. ● 4042 Clipper Ct. ● Fremont, CA 94538 ● Tel: 510 490-9160 ● Fax: 510 353-0261

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