AD7524UE Просмотр технического описания (PDF) - Analog Devices

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AD7524UE

CMOS 8-Bit Buffered Multiplying DAC

Analog Devices 

AD7524

CIRCUIT DESCRIPTION

CIRCUIT INFORMATION

The AD7524, an 8-bit multiplying D/A converter, consists of a

highly stable thin film R-2R ladder and eight N-channel current

switches on a monolithic chip. Most applications require the

addition of only an output operational amplifier and a voltage

or current reference.

The simplified D/A circuit is shown in Figure 1. An inverted

R-2R ladder structure is used—that is, the binarily weighted

currents are switched between the OUT1 and OUT2 bus lines,

thus maintaining a constant current in each ladder leg indepen-

dent of the switch state.

Figure 1. Functional Diagram

EQUIVALENT CIRCUIT ANALYSIS

The equivalent circuit for all digital inputs LOW is shown in

Figures 2. In Figure 2 with all digital inputs LOW, the refer-

ence current is switched to OUT2. The current source ILEAKAGE

is composed of surface and junction leakages to the substrate

while the 1 current source represents a constant 1-bit cur-

256

rent drain through the termination resistor on the R-2R ladder.

The “ON” capacitance of the output N-channel switches is

120 pF, as shown on the OUT2 terminal. The “OFF” switch

capacitance is 30 pF, as shown on the OUT1 terminal. Analysis

of the circuit for all digital inputs high is similar to Figure 2

however, the “ON” switches are now on terminal OUT1, hence

the 120 pF appears at that terminal.

WRITE MODE

When CS and WR are both LOW, the AD7524 is in the

WRITE mode, and the AD7524 analog output responds to data

activity at the DB0–DB7 data bus inputs. In this mode, the

AD7524 acts like a nonlatched input D/A converter.

HOLD MODE

When either CS or WR is HIGH, the AD7524 is in the HOLD

mode. The AD7524 analog output holds the value correspond-

ing to the last digital input present at DB0–DB7 prior to WR or

CS assuming the HIGH state.

MODE SELECTION TABLE

CS

WR

Mode

DAC Response

L

L

Write

DAC responds to data bus

(DB0–DB7) inputs.

H

X

X

H

Hold

Hold

Data bus (DB0–DB7) is

Locked Out:

DAC holds last data present

when WR or CS assumed

HIGH state.

L = Low State, H = High State, X = Don't Care.

WRITE CYCLE TIMING DIAGRAM

Figure 2. AD7524 DAC Equivalent Circuit—All Digital

Inputs Low

INTERFACE LOGIC INFORMATION

MODE SELECTION

AD7524 mode selection is controlled by the CS and WR inputs.

Figure 3. Supply Current vs. Logic Level

Typical plots of supply current, IDD, versus logic input voltage,

VIN, for VDD = +5 V and VDD = +15 V are shown above.

–4–

REV. B

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