PCA9540 Просмотр технического описания (PDF) - Philips Electronics
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PCA9540 Datasheet PDF : 10 Pages
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Philips Semiconductors
2-channel I2C multiplexer
Product specification
PCA9540
AC CHARACTERISTICS
SYMBOL
PARAMETER
tpd
fSCL
tBUF
tHD:STA
Propagation delay from SDA to SDn or SCL to SCn
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
STANDARD-MODE
I2C-BUS
MIN
MAX
0.31
0
100
4.7
–
4.0
–
FAST-MODE
I2C-BUS
MIN
MAX
0.31
0
400
1.3
–
0.6
–
UNIT
ns
kHz
µs
µs
tLOW
LOW period of the SCL clock
4.7
–
1.3
–
µs
tHIGH
HIGH period of the SCL clock
4.0
–
0.6
–
µs
tSU:STA Set-up time for a repeated START condition
4.7
–
0.6
µs
Data hold time:
tHD:DAT
for CBUS compatible masters
for I2C-bus devices
5.0
–
02
–
–
–
µs
02
0.93
µs
tSU:DAT
tSU:STO
tr
Data set-up time
Set-up time for STOP condition
Rise time of both SDA and SCL signals
250
–
1004
–
ns
–
1000
20 + 0.1Cb5
300
ns
–
300
20 + 0.1Cb5
300
ns
tf
Fall time of both SDA and SCL signals
4.0
–
0.6
–
µs
Cb
Capacitive load for each bus line
400
–
400
pF
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical RON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. A fast-mode I2C bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line trmax + tSU:DAT = 1000 + 250 = 1250 ns (according to the standard-mode
I2C-bus specification) before the SCL line is released.
5. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
SCL
P
tHD;STA
S
tHD;DAT
tHIGH
tSU;DAT
tHD;STA
tSU;STA
Sr
Figure 8. Definition of timing on the I2C-bus
tSP
tSU;STO
P
SU00645
1999 Dec 15
7
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