MX86251 Просмотр технического описания (PDF) - Macronix International

Номер в каталоге

Компоненты Описание

производитель

MX86251

3D graphic chipset

Macronix International 

MX86251

2.11 Pin Description

PCI Bus Interface Pins:

Pin Name Pin No. Type

PRESET# 178

I

PCICLK 167

I

FRAME# 173

I

IRDY#

170

I

TRDY#

171

STO

DEVSEL# 169

STO

STOP#

172

STO

PAR

174

TO

Description

This input is PCI bus RESET#, it is an active low signal used to initialize the GUI

to a known state. The trailing edge of this input loads the power on strapping

inputs through MD0 to MD17 and PFXSWAP.

This input is the PCI bus clock. It is an 1X clock of 33MHz.

This input is FRAME#, it is low to indicate the GUI that a valid address is present

on the PCI address bus and a New bus cycle or Burst bus cycles are starting.

When sampling this signal low, GUI would latch the address and bus commands.

This input is Initiator RDY#, it is generated from an PCI Bus Master. When it is

low, IRDYB indicates that the Initiator is able to complete the current bus trans

action if and only if the TRDY# is also low.

This output is Target RDY#, it is generated by GUI if the current bus cycle

belongs to the GUI. When it is low, TRDY# indicates that the GUI is able to

complete the current bus transaction which already targeted onto it if and only if

the IRDY# is also low. It remains low until this current cycle ends,then goes into

high for one PCI clock cycle, after that then goes into tri-state.

This output is DEVSEL#. When driven low, it indicates that GUI will respond to

the current cycle. It remains low until this current cycle ends, then goes into high

for one PCI clock cycle, after that then goes into tri-state.

This output is STOP#. When driven low, it indicates that GUI will request the

current bus master to stop the current bus transfer.

There are two configurations about this signal. One is called disconnect. Under

this configuration, GUI will complete the current transaction as the last one. In

this case, STOP# will be active at the same time that TRDY# is active. The other

configuration is called retry. In this case, GUI just request the bus master to

terminate the current cycle and retry again. TRDY# will not be generated in this

cycle. Once asserted, it remains low until this current cycle ends then goes into

high for one PCI clock cycle, after that then goes into tri-state.

This output is PAR. It is only driven during PCI bus master doing read accesses

from GUI. When driven, it will provide an even parity across the AD[31:0], and

C/BE#[3:0]. This signal is an tri-state output.

P/N:PM0476

REV. 1.2 , FEB 11, 1998

10

Share Link: