MU9C2480A(1998) Просмотр технического описания (PDF) - Music Semiconductors

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MU9C2480A
(Rev.:1998)

LANCAMs®

Music Semiconductors 

MU9C2480A/L

OPERATIONAL CHARACTERISTICS Continued

CAM Status

Validity bits at all memory locations

Match and Full Flag outputs

IEEE 802.3–802.5 Input Translation

CAM/RAM Partitioning

Comparison Masking

Address register auto-increment or auto-decrement

Source and Destination Segment counters count ranges

Address register and Next Free Address register

Page Address and Device Select registers

Control register after reset (including CT15)

Persistent Destination for Command writes

Persistent Source for Command reads

Persistent Source and Destination for Data reads and writes

Operating Mode

Configuration Register set

/RESET Condition

Skip = 0, Empty = 1 (empty)

Enabled

Not translated

64 bits CAM, 0 bits RAM

Disabled

Disabled

00B to 11B; loaded with 00B

Contains all 0s

Contains all 0s (no change on software reset)

Contains 0008H

Instruction decoder

Status register

Comparand register

Standard

Foreground

Table 4: Device Control State after Reset

Address Register (AR)

The Address register points to the CAM memory location

to be operated upon when M@[AR] or M@aaaH is part of

the instruction. It can be loaded directly by using a TCO

AR instruction or indirectly by using an instruction requiring

an absolute address, such as “MOV aaaH,CR,V.” After

being loaded, the Address register value will then be used

for the next memory access referencing the Address register.

A reset sets the Address register to zero.

Control Register bits CT3 and CT2 set the Address register to

automatically increment or decrement (or not change) during

sequences of Command or Data cycles. The Address register

will change after executing an instruction that includes

M@[AR] or M@aaaH, or after a data access to the end limit

segment (as set in the Segment Control register) when the

persistent source or destination is M@[AR] or M@aaaH.

Either the Foreground or Background Address register will

be active, depending on which register set has been

selected, and only the active Address register will be written

to or read from.

Next Free Address Register (NF)

The LANCAM automatically stores the address of the first

empty memory location in the Next Free Address register,

which is then used as a memory address pointer for M@NF

operations. The Next Free Address register, shown in Table

10 on page 22, can be read using a TCO NF instruction. By

taking /EC LOW during the TCO NF instruction cycle, only

the device with /FI LOW and /FF HIGH will output the

contents of its Next Free Address register, which gives the

Next Free address in a system of daisy-chained devices. The

Next Free address may be read from a specific device in the

chain by setting the Device Select register to the value of the

desired device’s Page address and leaving /EC HIGH.

The Full Flag daisy chain causes only the device whose /FI

input is LOW and /FF output HIGH to respond to an

instruction using the Next Free address. After a reset, the

Next Free Address register is set to zero.

Status Register

The 32-bit Status register, shown in Table 11 on page 22, is

the default source for Command Read cycles. Bit 31 is the

internal Full flag, which will go LOW if the particular device

has no empty memory locations. Bit 30 is the internal

Multiple Match flag, which will go LOW if a Multiple match

was detected. Bit 29 and Bit 28 are the Skip and Empty

Validity bits, which reflect the validity of the last memory

location read. After a reset, the Skip and Empty bits will

read 11 until a read or move from memory has occurred.

The rest of the Status register down to bit 1 contains the

Page address of the device and the address of the Highest-

Priority match. After a reset or a no-match condition, the

match address bits will be all 1s. Bit 0 is the internal Match

flag, which will go LOW if a match was found in this

particular device.

Comparand Register (CR)

The 64-bit Comparand register is the default destination

for data writes and reads, using the Segment Control register

to select which 16-bit segment of the Comparand register is

to be loaded or read out. The persistent source and

destination for data writes and reads can be changed to the

mask registers or memory by SPS and SPD instructions.

During an automatic or forced compare, the Comparand

Rev. 1a

10

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