MT8888CSR Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT8888CSR

Integrated DTMF Transceiver with Intel Micro Interface

Zarlink Semiconductor Inc 

MT8888C

Data Sheet

EXPLANATION OF EVENTS

A)

TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.

B)

TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

C)

END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

D)

TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

E)

ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.

F)

END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

EXPLANATION OF SYMBOLS

Vin

ESt

St/GT

RX0-RX3

b3

b2

IRQ/CP

tREC

tREC

tID

tDO

tDP

tDA

tGTP

tGTA

DTMF COMPOSITE INPUT SIGNAL.

EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.

STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.

4-BIT DECODED DATA IN RECEIVE DATA REGISTER

DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A

VALID DTMF SIGNAL.

INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS

REGISTER IS READ.

INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STATUS REGISTER IS READ.

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.

MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.

MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.

TIME TO DETECT VALID FREQUENCIES PRESENT.

TIME TO DETECT VALID FREQUENCIES ABSENT.

GUARD TIME, TONE PRESENT.

GUARD TIME, TONE ABSENT.

Figure 9 - Description of Timing Events

7.0 DTMF Generator

The DTMF transmitter employed in the MT8888C is capable of generating all sixteen standard DTMF tone pairs

with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The

sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable

dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a

DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the

encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the

receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and

High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 94 Hz. The high group

frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB

to compensate for high group attenuation on long loops.

The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length

of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched

and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time

segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate

count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time

segments is fixed at 32, however, by varying the segment length as described above the frequency can also be

varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.

9

Zarlink Semiconductor Inc.

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